MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 439

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Figure 13-8
erator. A 5-bit down counter, clocked at the IMB clock rate, is used to create both the
high phase and the low phase of the QCLK signal. At the beginning of the high phase,
the 5-bit counter is loaded with the 5-bit PSH value. When the zero detector finds that
the high phase is finished, the QCLK is reset. A 3-bit comparator looks for a one’s com-
plement match with the 3-bit PSL value, which is the end of the low phase of the QCLK.
The PSA bit was maintained for software compatibility, but has no effect on QADC64.
The following equations define QCLK frequency:
The following are equations for calculating the QCLK high/low phases in Example 1:
The following are equations for calculating the QCLK high/low phases in Example 2:
Where:
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
• PSH = 0 to 31, the prescaler QCLK high cycles in QACR0
• PSL = 0 to 7, the prescaler QCLK low cycles in QACR0
• F
• FQCLK = QCLK frequency
SYS
The guideline for selecting PSH and PSL is select is to maintain ap-
proximately 50% duty cycle. So for prescaler values less then 16, or
PSH ~= PSL. For prescaler values greater than 16 keep PSL as large
as possible.
shows that the prescaler is essentially a variable pulse width signal gen-
= IMB clock frequency
FQCLK= 1 ÷ (High QCLK Time + Low QCLK Time)
Freescale Semiconductor, Inc.
High QCLK Time = (11 + 1) ÷ 40 x 10
High QCLK Time = (7 + 1) ÷ 32 x 10
Low QCLK Time = (7 + 1) ÷ 40 x 10
Low QCLK Time = (7 + 1) ÷ 32 x 10
For More Information On This Product,
High QCLK Time = (PSH + 1) ÷ F
Low QCLK Time = (PSL + 1) ÷ F
FQCLK = 1/(300 + 200) = 2 MHz
Go to: www.freescale.com
Rev. 15 October 2000
NOTE
6
6
6
6
= 200 ns
= 250 ns
SYS
= 250 ns
SYS
= 300 ns
MOTOROLA
13-27