MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 501

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.7.6.1 Description of Slave Operation
MPC555
USER’S MANUAL
After reset, the QSMCM registers and the QSPI control registers must be initialized as
described above. Although the command control segment is not used, the transmit
and receive data segments may, depending upon the application, need to be initial-
ized. If meaningful data is to be sent out from the QSPI, the user should write the data
to the transmit data segment before enabling the QSPI.
If SPE is set and MSTR is not set, a low state on the slave select (PCS[0]/SS) pin com-
mences slave mode operation at the address indicated by NEWQP. The QSPI trans-
mits the data found in the transmit data segment at the address indicated by NEWQP,
and the QSPI stores received data in the receive data segment at the ad-dress indi-
cated by NEWQP. Data is transferred in response to an external slave clock input at
the SCK pin.
Because the command control segment is not used, the command control bits and pe-
ripheral chip-select codes have no effect in slave mode operation. The QSPI does not
drive any of the four peripheral chip-selects as outputs. PCS[0]/SS is used as an input.
Although CONT cannot be used in slave mode, a provision is made to enable receipt
of more than 16 data bits. While keeping the QSPI selected (PCS[0]/SS is held low),
the QSPI stores the number of bits, designated by BITS, in the current receive data
segment address, increments NEWQP, and continues storing the remaining bits (up
to the BITS value) in the next receive data segment address.
As long as PCS[0]/SS remains low, the QSPI continues to store the incoming bit
stream in sequential receive data segment addresses, until either the value in BITS is
reached or the end-of-queue address is used with wraparound mode disabled.
When the end of the queue is reached, the SPIF flag is asserted, optionally causing
an interrupt. If wraparound mode is disabled, any additional incoming bits are ignored.
If wraparound mode is enabled, storing continues at either address 0x0 or the address
of NEWQP, depending on the WRTO value. When using this capability to receive a
long incoming data stream, the proper delay between transfers must be used. The
QSPI requires time, approximately 0.425 µs with a 40-MHz IMB clock, to prefetch the
next transmit RAM entry for the next transfer. Therefore, the user may select a baud
rate that provides at least a 0.6-µs delay between successive transfers to ensure no
loss of incoming data. If the IMB clock is operating at a slower rate, the delay between
transfers must be increased proportionately.
Because the BITSE option in the command control segment is no longer available,
BITS sets the number of bits to be transferred for all transfers in the queue until the
CPU changes the BITS value. As mentioned above, until PCS[0]/SS is negated
(brought high), the QSPI continues to shift one bit for each pulse of SCK. If PCS[0]/SS
is negated before the proper number of bits (according to BITS) is received, the next
time the QSPI is selected it resumes storing bits in the same receive-data segment ad-
dress where it left off. If more than 16 bits are transferred before negating the PCS[0]/
SS, the QSPI stores the number of bits indicated by BITS in the current receive data
segment address, then increments the address and continues storing as described
/
MPC556
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
14-39