MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 149

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

3.9.10.3 Additional Implementation-Specific Registers
MPC555
USER’S MANUAL
FPECR — Floating-Point Exception Cause Register
Bit(s)
[1:27]
MSB
SIE
16
28
29
30
31
0
0
0
0
RESET:
RESET:
Refer to the following sections for details on additional implementation-specific regis-
ters in the MPC555 / MPC556:
A listing of FPECR bit descriptions is shown in
•
•
•
•
17
/
1
0
0
4.6 Burst Buffer Programming Model
6.13.1.2 Internal Memory Map Register
11.8 L2U Programming Model
SECTION 21 DEVELOPMENT SUPPORT
Name
MPC556
DNC
DNB
DNA
SIE
TR
—
18
2
0
0
Software must insert a sync instruction before reading the FPECR.
SIE mode control bit
0 = Disable SIE mode
1 = Enable SIE mode
Reserved
Source operand C denormalized status bit
0 = Source operand C is not denormalized
1 = Source operand C is denormalized
Source operand B denormalized status bit
0 = Source operand B is not denormalized
1 = Source operand B is denormalized
Source operand A denormalized status bit
0 = Source operand A is not denormalized
1 = Source operand A is denormalized
Floating-point tiny result
0 = Floating-point result is not tiny
1 = Floating-point result is tiny
19
3
0
0
Freescale Semiconductor, Inc.
20
4
0
0
For More Information On This Product,
Table 3-18 FPECR Bit Descriptions
RESERVED
21
5
0
0
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
22
6
0
0
23
7
0
0
RESERVED
NOTE
24
8
0
0
Description
25
9
0
0
Table
10
26
0
0
3-18.
11
27
0
0
DNC
12
28
0
0
DNB
13
29
0
0
SPR 1022
MOTOROLA
DNA
14
30
0
0
LSB
TR
15
31
3-27
0
0