MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 391

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

11.5.2 Associated Registers
MPC555
USER’S MANUAL
When more than one match indication occurs, the effective region is the region with
the highest priority. Priority is determined by region number; highest priority corre-
sponds to the lowest region number.
When no match occurs, the effective region is the global region. The global region has
the lowest priority.
The region attribute register also contains the region’s protection fields. The protection
field (PP) of the effective region is compared to the access attributes. If the attributes
match, the access is permitted. When the access is permitted, a U-bus access may be
generated according to the specific attribute of the effective region.
When the access by the RCPU is not permitted, the L2U module asserts a data mem-
ory storage exception to the RCPU.
For speculative load/store accesses from the RCPU to a region marked as guarded
(G bit of region attribute register is set), the L2U asks the RCPU to retry the L-bus cycle
until either the access is not speculative, or it is canceled by the RCPU.
In the case of attempted accesses to a guarded region together with any other protec-
tion violation (no access), the L2U retries the access. The L2U handles this event as
a data storage violation only when the access becomes non-speculative.
Note that access protection is active only when the PowerPC’s MSR[DR] = 1. When
MSR[DR] = 0, DMPU exceptions are disabled, all accesses are considered to be to a
guarded memory area, and no speculative accesses are allowed. In this case, if the L-
bus master [RCPU] initiates a non-SRAM cycle (access through the L2U) that is
marked speculative, the L2U asks the RCPU to retry the L-bus cycle until either the
access is not speculative, or it is canceled by the RCPU core.
Note that the programmer must not overlap the SRAM memory space with any en-
abled region. Overlapping an enabled region with SRAM memory space disables the
L2U data memory protection for that region.
If an enabled region overlaps with the L-bus space, the DMPU ignores all accesses to
addresses within the L-bus space. If an enabled region overlaps with PowerPC regis-
ter addresses, the DMPU ignores any access marked as a PowerPC access.
The following registers are used to control the DMPU of the L2U module. All the reg-
isters are special purpose registers which are accessed via the PowerPC mtspr/mf-
spr instructions. The registers are also accessed by an external master when
EMCR[CONT] = 0. See
descriptions.
/
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
11.8 L2U Programming Model
L-BUS TO U-BUS INTERFACE (L2U)
Go to: www.freescale.com
Rev. 15 October 2000
for register diagrams and bit
MOTOROLA
11-5