MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 277

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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MPC555LFMZP40
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8.8.3.1 Exiting from Normal-Low Mode
8.8.3.2 Exiting from Doze Mode
8.8.3.3 Exiting from Deep-Sleep Mode
MPC555
USER’S MANUAL
decrementer exception is only three to four clock cycles of maximum system frequen-
cy. In 40-MHz systems, this wake-up requires 75 to 100 ns. The asynchronous wake-
up interrupt from the interrupt controller is level sensitive one. It will therefore be ne-
gated only after the reset of interrupt cause in the interrupt controller.
The timers (RTC, PIT, time base, or decrementer) interrupts indication set status bits
in the PLPRCR (TMIST). The clock module considers this interrupt to be pending
asynchronous interrupt as long as the TMIST is set. The TMIST status bit should be
cleared before entering any low-power mode.
Table 8-7
In normal mode (as well as doze mode), if the PLPRCR[CSRC] bit is set, the system
toggles between low frequency (defined by PLPRCR[DFNL]) and high frequency (de-
fined by PLPRCR[DFNH]. The system switches from normal-low mode to normal-high
mode if either of the following conditions is met:
When neither of these conditions are met, the PLPRCR[CSRC] bit is set, and the asyn-
chronous interrupt status bits are reset, the system returns to normal-low mode.
The system changes from doze mode to normal-high mode whenever an interrupt is
pending from the interrupt controller.
The system switches from deep-sleep mode to normal-high mode if any of the follow-
ing conditions is met:
• An interrupt is pending from the interrupt controller; or
• The MSR[POW] bit is cleared (power management is disabled).
/
MPC556
summarizes wake-up operation for each of the low-power modes.
Normal-low (“gear”)
Operation Mode
Power-down
Deep-sleep
Doze-high
Doze-low
V
Table 8-6 Power Mode Wake-Up Operation
DDSRAM
Sleep
Freescale Semiconductor, Inc.
For More Information On This Product,
CLOCKS AND POWER CONTROL
Go to: www.freescale.com
Rev. 15 October 2000
Wake-up
Software
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
External
Method
or
< 500 oscillator cycles + power
Return Time from Wake-up
3-4 maximum system cycles
3-4 maximum system clocks
Asynchronous interrupts:
3-4 actual system cycles
Synchronous interrupts:
< 500 Oscillator Cycles
Event to Normal-High
Power-on sequence
125 µsec – 4 MHz
25 µsec – 20 MHz
supply wake-up
MOTOROLA
8-17

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