MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 592

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

16.3.5 Time Stamp
MPC555
USER’S MANUAL
Both counters are read-only (except in test/freeze/halt modes).
The TouCAN responds to any bus state as described in the CAN protocol, transmitting
an error active or error passive flag, delaying its transmission start time (error passive)
and avoiding any influence on the bus when in the bus off state. The following are the
basic rules for TouCAN bus state transitions:
The value of the free-running 16-bit timer is sampled at the beginning of the identifier
field on the CAN bus. For a message being received, the time stamp is stored in the
time stamp entry of the receive message buffer at the time the message is written into
• Rx error counter reset to a value between 119 and 127 inclusive, when the Tou-
• Following reset, both counters reset to zero
• Detect values for error passive, bus off and error active transitions
• Cascade usage of Tx error counter with an additional internal counter to detect
• If the value of the Tx error counter or Rx error counter increments to a value great-
• If the TouCAN is in an error passive state, and either the Tx error counter or Rx
• If the value of the Tx error counter increases to a value greater than 255, the
• If the TouCAN is in the bus off state, the Tx error counter and an additional inter-
• If only one node is operating in a system, the Tx error counter is incremented with
• If the Rx error counter increments to a value greater than 127, it stops increment-
/
CAN transitions from error passive to error active
the 128 occurrences of 11 consecutive recessive bits necessary to transition from
bus off into error active.
er than or equal to 128, the fault confinement state (FCS[1:0]) field in the error sta-
tus register is updated to reflect an error passive state.
error counter decrements to a value less than or equal to 127 while the other error
counter already satisfies this condition, the FCS[1:0] field in the error status reg-
ister is updated to reflect an error active state.
FCS[1:0] field in the error status register is updated to reflect a bus off state, and
an interrupt may be issued. The value of the Tx error counter is reset to zero.
nal counter are cascaded to count 128 occurrences of 11 consecutive recessive
bits on the bus. To do this, the Tx error counter is first reset to zero, and then the
internal counter begins counting consecutive recessive bits. Each time the inter-
nal counter counts 11 consecutive recessive bits, the Tx error counter is incre-
mented by one and the internal counter is reset to zero. When the Tx error counter
reaches the value of 128, the FCS[1:0] field in the error status register is updated
to be error active, and both error counters are reset to zero. Any time a dominant
bit is detected following a stream of less than 11 consecutive recessive bits, the
internal counter resets itself to zero but does not affect the Tx error counter value.
each message it attempts to transmit, due to the resulting acknowledgment er-
rors. However, acknowledgment errors never cause the TouCAN to change from
the error passive state to the bus off state.
ing, even if more errors are detected while being a receiver. After the next suc-
cessful message reception, the counter is reset to a value between 119 and 127,
to enable a return to the error active state.
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
CAN 2.0B CONTROLLER MODULE
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
16-10