MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 324

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.5.5 Alignment and Packaging of Transfers
MPC555
USER’S MANUAL
The MPC555 / MPC556 external bus requires natural address alignment:
The MPC555 / MPC556 performs operand transfers through its 32-bit data port. If the
transfer is controlled by the internal memory controller, the MPC555 / MPC556 can
support 8- and 16-bit data port sizes.
The bus requires that the portion of the data bus used for a transfer to or from a par-
ticular port size be fixed. A 32-bit port must reside on DATA[0:31], a 16-bit port must
reside on DATA[0:15], and an 8-bit port must reside on DATA[0:7]. The MPC555 /
MPC556 always tries to transfer the maximum amount of data on all bus cycles. For a
word operation, it always assumes that the port is 32 bits wide when beginning the bus
cycle.
In
used:
Figure 9-22
Figure
• Byte accesses allow any address alignment
• Half-word accesses require address bit 31 to equal zero
• Word accesses require address bits 30 – 31 to equal zero
• Burst accesses require address bits 30 – 31 to equal zero
• OP0 is the most-significant byte of a word operand and OP3 is the least-signifi-
• The two bytes of a half-word operand are either OP0 (most-significant) and OP1
• The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending
0
/
cant byte.
or OP2 (most-significant) and OP3, depending on the address of the access.
on the address of the access.
MPC556
9-21,
OP0
OP0
OP0
illustrates the device connections on the data bus.
Figure
Figure 9-21 Internal Operand Representation
Freescale Semiconductor, Inc.
For More Information On This Product,
9-22,
OP1
OP1
OP1
EXTERNAL BUS INTERFACE
Table
Go to: www.freescale.com
Rev. 15 October 2000
9-2, and
OP2
OP2
OP2
Table
9-3, the following conventions are
OP3
OP3
OP3
31
Word
Half-word
Byte
MOTOROLA
9-28