MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 481

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

SPCR3 — QSPI Control Register
SPCR2 — QSPI Control Register 2
14.7.1.4 QSPI Control Register 3
MPC555
USER’S MANUAL
RESET:
MSB
SPIFIE WREN WRTO
Bit(s)
11:15
8:10
MSB
3:7
0
0
RESET:
0
1
2
0
0
SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enable, and
the halt control bit. The CPU has read/write access to SPCR3, but the QSPI has read
access only. SPCR3 must be initialized before QSPI operation begins. Writing a new
value to SPCR3 while the QSPI is enabled disrupts operation.
*See bit descriptions in
1
0
/
NEWQP
ENDQP
SPIFIE
1
0
WREN
WRTO
MPC556
Name
Reserved
—
2
0
2
0
SPI finished interrupt enable. Refer to
0 = QSPI interrupts disabled
1 = QSPI interrupts enabled
Wrap enable. Refer to
0 = Wraparound mode disabled.
1 = Wraparound mode enabled.
Wrap to. When wraparound mode is enabled and after the end of queue has been reached,
WRTO determines which address the QSPI executes next. The end of queue is determined by
an address match with ENDQP.
0 = Wrap to pointer address 0x0
1 = Wrap to address in NEWQP
Ending queue pointer. This field determines the last absolute address in the queue to be com-
pleted by the QSPI. After completing each command, the QSPI compares the queue pointer val-
ue of the just-completed command with the value of ENDQP. If the two values match, the QSPI
sets SPIF to indicate it has reached the end of the programmed queue. Refer to
Operation
Reserved
New queue pointer value. This field contains the first QSPI queue address. Refer to
Operation
3
0
3
0
Table
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
4
0
Table 14-16 SPCR2 Bit Descriptions
For More Information On This Product,
4
0
for more information.
for more information.
14-18.
LOOP
ENDQP
Q
5
0
5
0
Go to: www.freescale.com
14.7.5.7 Master Wraparound
HMIE
Rev. 15 October 2000
6
0
6
0
HALT
7
0
7
0
14.7.4.2 QSPI
8
8
0
Description
Reserved
9
9
0
Interrupts.
Mode.
10
10
0
11
11
0
SPSR*
12
12
0
NEWQP
13
13
0
0x30 501C
0x30 501E
14.7.4 QSPI
MOTOROLA
14.7.4 QSPI
14
14
0
14-19
LSB
LSB
15
15
0