MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 400

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

11.8.4 Region Base Address Registers (L2U_RBAx)
x = Undefined
MPC555
USER’S MANUAL
L2U_RBAx — L2U Region x Base Address Register
Bit(s)
Bit(s)
20:31
MSB
3:31
0:19
1:2
16
0
x
x
0
RESET:
RESET:
The region base address register defines the base address of a specific region pro-
tected by the data memory protection unit. There are four registers (x = 0...3), one for
each supported region.
17
/
1
x
x
LSHOW
MPC556
Name
Name
RBA
RBA
SP
—
—
18
2
x
x
SRAM Protection (SP) bit is used to protect the SRAM on the L-bus from U-bus accesses.
This bit can be set or cleared from the L-bus side. It can be set or cleared from the U-bus side
when factory test mode is enabled. When not in factory test mode, any attempt to set or clear the
SP bit from the U-bus side has no affect.
Once this bit is set, the L2U blocks all SRAM accesses initiated by the U-bus masters and the
access is terminated with a data error on the U-bus.
If L-bus show cycles are enabled, setting this bit will disable L-bus SRAM show cycles.
LSHOW bits are used to configure the show cycle mode for cycles accessing the L-bus slave e.g.
SRAM
00 = Disable show cycles
01 = Show address and data of all L-bus space write cycles
10 = Reserved
11 = Show address and data of all L-bus space read and write cycles
Reserved
Region base address. The RBA field provides the base address of the region. The region base
address should start on the block boundary for the corresponding block size attribute specified
in the region attribute register (L2U_RAx).
Reserved
19
3
x
x
Freescale Semiconductor, Inc.
Table 11-8 L2U_RBAx Bit Descriptions
Table 11-7 L2U_MCR Bit Descriptions
20
4
x
0
For More Information On This Product,
L-BUS TO U-BUS INTERFACE (L2U)
21
5
x
0
Go to: www.freescale.com
Rev. 15 October 2000
22
6
x
0
23
7
x
0
RBA
24
8
x
0
Description
Description
RESERVED
25
9
x
0
10
26
x
0
11
27
x
0
12
28
x
0
SPR 792 – 795
13
29
x
0
MOTOROLA
14
30
x
0
11-14
LSB
15
31
x
0