MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 332

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.5.7.1 Transfer Start
9.5.7.2 Address Bus
9.5.7.3 Read/Write
9.5.7.4 Burst Indicator
MPC555
USER’S MANUAL
This signal (TS) indicates the beginning of a transaction on the bus addressing a slave
device. This signal should be asserted by a master only after the ownership of the bus
was granted by the arbitration protocol. This signal is asserted for the first cycle of the
transaction only and is negated in successive clock cycles until the end of the trans-
action. The master should three-state this signal when it relinquishes the bus to avoid
contention between two or more masters in this line. This situation indicates that an
external pull-up resistor should be connected to the TS signal to avoid having a slave
recognize this signal as asserted when no master drives it. Refer to
The address bus consists of 32 bits, with ADDR[0] the most significant bit and AD-
DR[31] the least significant bit. The bus is byte-addressable, so each address can ad-
dress one or more bytes. The address and its attributes are driven on the bus with the
transfer start signal and kept valid until the bus master receives the transfer acknowl-
edge signal from the slave. To distinguish the individual byte, the slave device must
observe the TSIZ signals.
A high value on the RD/WR line indicates a read access. A low value indicates a write
access.
BURST is driven by the bus master at the beginning of the bus cycle along with the
address to indicate that the transfer is a burst transfer.
The MPC555 / MPC556 supports a non-wrapping, four-beat maximum, critical word
first burst type. The maximum burst size is 16 bytes. For a 32-bit port, the burst in-
cludes four beats. For a 16-bit port, the burst includes 8 beats. For an 8-bit port, the
burst includes 16 beats at most. Note that 8- and 16-bit ports must be controlled by the
memory controller.
The actual size of the burst is determined by the address of the starting word of the
burst. Refer to
ADDR[28:29]
Address
Starting
00
01
10
11
/
MPC556
word 1 → word 2 → word 3
Burst Order (Assuming
Table 9-5
word 0 → word 1 →
word 2 → word 3
32-bit Port Size)
word 2 → word 3
Freescale Semiconductor, Inc.
word 3
For More Information On This Product,
Table 9-5 Burst Length and Order
and
EXTERNAL BUS INTERFACE
Go to: www.freescale.com
Table
Rev. 15 October 2000
Burst Length in
Words (Beats)
9-6.
4
3
2
1
Burst Length
in Bytes
16
12
8
4
BDIP never asserted
Comments
Figure
MOTOROLA
9-24.
9-36