MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 406

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

12.4.1 Interrupt Sources and Levels on IMB
12.4.2 IMB Interrupt Multiplexing
12.4.3 ILBS Sequencing
MPC555
USER’S MANUAL
Byte-enable
The IMB3 has eight interrupt lines. There can be a maximum of 32 levels of interrupts
from the modules on IMB bus. A single module can be a source for more than one in-
terrupt. For example, the QSMCM can generate two interrupts (one for QSCI1/QSCI2
and another for QSPI). In this case, the QSMCM has two interrupt sources. Each of
these two sources can assert the interrupt on any of the 32 levels.
It is possible for multiple interrupt sources to assert the same interrupt level. To reduce
the latency, it is a good practice for each interrupt source to assert an interrupt on a
level on which no other interrupt source is mapped.
The IMB has 10 lines for interrupt support. Eight lines are for interrupts and two for
ILBS. These lines will transfer the 32 interrupt levels to the interrupt synchronizer. A
diagram of the interrupt flow is shown in
Latching 32 interrupt levels using eight IMB interrupt lines is accomplished with a 4:1
time-multiplexing scheme. The UIMB drives two signals (ILBS[0:1]) with a multiplexer
select code that tells all interrupting modules on the IMB about which group of signals
to drive during the next clock.
The IMB interface drives the ILBS signals continuously, incrementing through a code
sequence (00, 01, 10, 11) once every clock The IRQMUX[0:1] bits in the IMB module
configuration register select which type of multiplexing the Interrupt synchronizer will
perform. The IRQMUX field can select time-multiplexing protocols for 8, 16, 24 or 32
interrupt sources. These protocols would take one, two, three or four clocks, respec-
tively.
to IMB
/
MPC556
2
Byte Count
Figure 12-4 Interrupt Synchronizer Signal Flow
Block
Freescale Semiconductor, Inc.
For More Information On This Product,
U-BUS TO IMB3 BUS INTERFACE (UIMB)
IMB interrupt
Byte-enables
Go to: www.freescale.com
Rev. 15 October 2000
4
8
Figure
(24:31)
(16:23)
UIPEND
(8:15)
(0:7)
12-4.
8
U-bus Data[0:31]
U-bus Interrupt
Level[0:7]
MOTOROLA
12-4