MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 757

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

22.3 Operating Frequency
22.4 TAP Controller
MPC555
USER’S MANUAL
Signal
Name
TRST
TDO
TMS
TCK
TDI
The TCK frequency must be between 5 MHz and 10 MHz. This pin is internally driven
to a low value when disconnected.
TRST is used to reset the TAP controller asynchronously. The TRST pin ensures that
the JTAG logic does not interfere with the normal operation of the chip. This pin is op-
tional in the JTAG specification.
The TAP controller changes state either on the rising edge of TCK or when TRST is
asserted.
The TDO signal remains in a high-impedance state except during the Shift-DR or Shift-
IR controller states. During these controller states, TDO is updated on the falling edge
of TCK.
The TAP controller states are designed to meet the IEEE 1149.1 standard. Refer to
Figure
/
Output (I/O)
MPC556
22-3.
Output
Input/
Input
Input
Input
Input
Table 22-1 JTAG Interface Pin Descriptions
Pull-Down Provided
Freescale Semiconductor, Inc.
Internal Pull-Up/
IEEE 1149.1-COMPLIANT INTERFACE (JTAG)
For More Information On This Product,
Pull-down
Pull-up
Pull-up
Pull-up
None
Go to: www.freescale.com
Rev. 15 October 2000
Test data input pin. Sampled on the rising edge of TCK. Has a
pull-up resistor.
Test data output pin. Actively driven during the Shift-IR and Shift-
DR controller states. Changes on the falling edge of TCK. Can
be placed in high-impedance state.
Test mode select pin. Sampled on the rising edge of TCK to se-
quence the test controller’s state machine. Has a pull-up resis-
tor.
Test clock input to synchronize the test logic. Has a pull-down re-
sistor.
TAP controller asynchronous reset. Provides initialization of the
TAP controller and other logic as required by the standard. Has
a pull-up resistor.
Description
MOTOROLA
22-3