MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 574

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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MIOS1RPR1 — MIRSM1 Request Pending Register
15.15 MIOS1 Function Examples
15.15.1 MIOS1 Input Double Edge Pulse Width Measurement
MPC555
USER’S MANUAL
IRP31 IRP30 IRP29 IRP28 IRP27
MSB
0
0
RESET:
The versatility of the MIOS1 timer architecture is based on multiple counters and cap-
ture/compare channel units interconnected on 16-bit counter buses. This section in-
cludes some typical application examples to show how the submodules can be
interconnected to form timing functions. The diagrams used to illustrate these exam-
ples show only the blocks utilized for that function.
To illustrate the timing range of the MIOS1 in different applications, many of the follow-
ing paragraphs include time intervals quoted in microseconds and seconds. The as-
sumptions used are that f
cycle) and with the maximum overall prescaling (32 µs cycle). For other f
cle rates and prescaler choices, the times mentioned in these paragraphs scale appro-
priately.
To measure the width of an input pulse, the MIOS double action submodule (MDASM)
has two capture registers so that only one interrupt is needed after the second edge.
The software can read both edge samples and subtract them to get the pulse width.
The leading edge sample is double latched so that the software has the time of one
full period of the input signal to read the samples to be sure that nothing is lost. De-
pending on the prescaler divide ratio, pulse width from 50 ns to 6.7 s can be mea-
sured. Note that a software option is provided to also generate an interrupt after the
first edge.
1
0
/
MPC556
2
0
Bit(s)
10:11
5:8
12
13
14
15
0
1
2
3
4
9
3
0
Table 15-35 MIOS1RPR1 Bit Descriptions
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Freescale Semiconductor, Inc.
4
0
IRP31
IRP30
IRP29
IRP28
IRP27
IRP22
IRP19
IRP18
IRP17
IRP16
For More Information On This Product,
Name
5
0
SYS
Go to: www.freescale.com
MDASM31 IRQ pending bit
MDASM30 IRQ pending bit
MDASM29 IRQ pending bit
MDASM28 IRQ pending bit
MDASM27 IRQ pending bit
Reserved
MMCSM22 IRQ pending bit
Reserved
MPWMSM19 IRQ pending bit
MPWMSM18 IRQ pending bit
MPWMSM17 IRQ pending bit
MPWMSM16 IRQ pending bit
is at 40 MHz with minimum overall prescaling (50 ns
RESERVED
Rev. 15 October 2000
6
0
7
0
8
0
Description
IRP22
9
0
RESERVED
10
0
11
0
IRP19 IRP18 IRP17 IRP16
12
0
13
0
SYS
0x30 6C46
MOTOROLA
14
clock cy-
0
15-38
LSB
15
0

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