MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 637

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

17.4.11 Channel Interrupt Status Register
CISR — Channel Interrupt Status Register
17.4.12 Link Register
LR — Link Register
17.4.13 Service Grant Latch Register
SGLR — Service Grant Latch Register
17.4.14 Decoded Channel Number Register
DCNR — Decoded Channel Number Register
MPC555
USER’S MANUAL
CH 15 CH 14 CH 13 CH 12 CH 11 CH 10
Bit(s)
MSB
0:15
0
0
RESET:
The channel interrupt status register (CISR) contains one interrupt status flag per
channel. Time functions specify via microcode when an interrupt flag is set. Setting a
flag causes the TPU3 to make an interrupt service request if the corresponding CIER
bit is set. To clear a status flag, read CISR, then write a zero to the appropriate bit.
CISR is the only TPU3 register that can be accessed on a byte basis.
Used for factory test only.
Used for factory test only.
Used for factory test only.
1
0
/
CH[15:0]
MPC556
Name
2
0
Channel interrupt status
0 = Channel interrupt not asserted
1 = Channel interrupt asserted
3
0
Freescale Semiconductor, Inc.
CHx[1:0]
4
0
For More Information On This Product,
Table 17-16 CISR Bit Descriptions
00
01
10
11
Table 17-15 Channel Priorities
5
0
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
CH 9
Rev. 15 October 2000
Disabled
Service
6
0
Middle
High
Low
CH 8
7
0
CH 7
Guaranteed Time Slots
8
0
Description
CH 6
1 out of 7
2 out of 7
4 out of 7
9
0
—
CH 5
10
0
CH 4
11
0
0x30 4022, 0x30 4422
0x30 4024, 0x30 4424
0x30 4026, 0x30 4426
CH 3
12
0
CH 2
13
0
0x30 4020
0x30 4420
MOTOROLA
CH 1
14
0
17-19
CH 0
LSB
15
0