MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 143

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Bit(s)
0:12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
/
MPC556
Name
POW
FE0
FE1
ILE
ME
EE
PR
SE
BE
DR
FP
—
—
—
IP
IR
Reserved
Power management enable
0 = Power management disabled (normal operation mode)
1 = Power management enabled (reduced power mode)
Reserved
Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to select
the endian mode for the context established by the exception.
0 = Processor runs in big-endian mode during exception processing.
1 = Processor runs in little-endian mode during exception processing.
External interrupt enable. Interrupts should only be negated while the EE bit is disabled (0). Soft-
ware should disable interrupts in the CPU core prior to masking or disabling any interrupt which
might be currently pending at the CPU core. For external interrupts, it is recommended that the
edge triggered interrupt scheme be used.
0 = The processor delays recognition of external interrupts and decrementer exception condi-
1 = The processor is enabled to take an external interrupt or the decrementer exception.
Privilege level
0 = The processor can execute both user- and supervisor-level instructions.
1 = The processor can only execute user-level instructions.
Floating-point available
0 = The processor prevents dispatch of floating-point instructions, including floating-point loads,
1 = The processor can execute floating-point instructions, and can take floating-point enabled ex-
Machine check enable
0 = Machine check exceptions are disabled.
1 = Machine check exceptions are enabled.
Floating-point exception mode 0 (See
Single-step trace enable
0 = The processor executes instructions normally.
1 = The processor generates a single-step trace exception upon the successful execution of the
Branch trace enable
0 = No trace exception occurs when a branch instruction is completed
1 = Trace exception occurs when a branch instruction is completed
Floating-point exception mode 1 (See
Reserved
Exception prefix. The setting of this bit specifies the location of the exception vector table.
0 = Exception vector table starts at the physical address 0x0000 0000.
1 = Exception vector table starts at the physical address 0xFFF0 0000.
Instruction relocation.
0 = Instruction address translation is off, the BBC IMPU does not check for address permission
1 = Instruction address translation is on, the BBC IMPU checks for address permission attributes.
Data relocation
0 = Data address translation is off, the L2U DMPU does not check for address permission at-
1 = Data address translation is on, the L2U DMPU checks for address permission attributes.
Table 3-12 Machine State Register Bit Descriptions
tions.
stores and moves. Floating-point enabled program exceptions can still occur and the FPRs
can still be accessed.
ception type program exceptions.
next instruction. When this bit is set, the processor dispatches instructions in strict program
order. Successful execution means the instruction caused no other exception. Single-step
tracing may not be present on all implementations.
tributes.
attributes.
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
Table
Table
Description
3-13.)
3-13.)
MOTOROLA
3-21