MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 52

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

1.2 MPC555 / MPC556 Features
1.2.1 RISC MCU Central Processing Unit (RCPU)
MPC555
USER’S MANUAL
Features of each module on the MPC555 / MPC556 are listed below.
• 32-bit PowerPC architecture (compliant with PowerPC Architecture Book 1)
• Core performance measured at 52.7 Kmips (Dhrystone 2.1) @ 40 MHz.
• Fully static, low power operation
• Integrated floating-point unit
• Precise exception model
• Extensive system development support
/
— On-chip watchpoints and breakpoints
— Program flow tracking
MPC556
RCPU
QADC
TPU3
This assumes the RCPU core is running in “normal” mode and show
cycles is turned off (ISCT_SER of the ICTRL register is set to 111).
See
Table
Figure 1-1 MPC555 / MPC556 Block Diagram
DPTRAM
QADC
Freescale Semiconductor, Inc.
16 Kbytes
21-21.
SRAM
For More Information On This Product,
Interface
Burst
QSMCM
TPU3
L-bus
Go to: www.freescale.com
Rev. 15 October 2000
10 Kbytes
256 Kbytes
SRAM
OVERVIEW
Flash
TouCAN
TouCAN
NOTE
MIOS1
192 Kbytes
Flash
L2U
U-bus
UIMB
USIU
IMB3
MOTOROLA
E-bus
1-2