MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 671

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
5. Write to the 64-byte array locations to be programmed. This updates the pro-
6. Write EHV = 1 in the CMFCTL register.
7. Read the CMFCTL register until HVS = 0.
8. Write EHV = 0.
9. To verify the programming, read the words of the pages that are being pro-
/
MPC556
gramming page buffer(s) with the information to be programmed. The last write
to a word within the program page buffer will be saved for programming. All ac-
cesses of the array after the first write are to the same block offset address
(ADDR[17:25]) regardless of the address provided. Thus the locations access-
ed after the first programming write are limited to the page locations to be pro-
grammed. Off-page read accesses of the CMF array after the first programming
write are program margin reads. (See section
To select the CMF EEPROM array block(s) to be programmed, the program
page buffers use the CMF EEPROM array configuration and BLOCK[0:7]. Sub-
sequent writes fill in the programming page buffers using the block address to
select the program page buffer and the page word address (ADDR[26:29]) to
select the word in the page buffer.
grammed. These are program margin reads. (See
Reads.) If any bit is a 1 after reading all of the locations that are being pro-
grammed, then another pulse needs to be applied to the these locations. If all
the locations verify as programmed go to step 11.
To reduce the time for verification, read two locations in each program page that
is being programmed after reading a non-programmed bit. The first location
must be a location with ADDR[26] = 0, while the second must use ADDR[26] =
1. In addition, after a location has been fully verified (all bits are programmed)
it is not necessary to verify the location again, since no further programming
voltages will be applied to the drain of the corresponding bits. This will reduce
the time required to program the array.
If a program buffer word has not received a programming write no
programming voltages will be applied to the drain of the correspond-
ing word in the array. Also, at this point writes to the program page
buffers are disabled until SES has been cleared and set.
After a program pulse, read at least one location with ADDR[26] = 0
and one location with ADDR[26] = 1 on each programmed page. Fail-
ure to do so may result in the loss of information in the CMF
EEPROM array. While this will not physically damage the array a full
erase of all blocks being programmed must be done before the CMF
EEPROM can be used reliably. For more information see
Over-Programming.
Freescale Semiconductor, Inc.
For More Information On This Product,
CDR MoneT FLASH EEPROM
Go to: www.freescale.com
Rev. 15 October 2000
WARNING
NOTE
19.5.2 Program Margin
19.5.2 Program Margin
19.5.3
MOTOROLA
Reads.)
19-19