MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 148

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

3.9.10 Implementation-Specific SPRs
3.9.10.1 EIE, EID, and NRI Special-Purpose Registers
3.9.10.2 Floating-Point Exception Cause Register (FPECR)
MPC555
USER’S MANUAL
Bit(s)
16:31
0:15
The MPC555 / MPC556 includes several implementation-specific SPRs that are not
defined by the PowerPC architecture. These registers can be accessed by supervisor-
level instructions only. These registers are listed in
The RCPU includes three implementation-specific SPRs to facilitate the software ma-
nipulation of the MSR[RI] and MSR[EE] bits. Issuing the mtspr instruction with one of
these registers as an operand causes the RI and EE bits to be set or cleared as shown
in
A read (mfspr) of any of these locations is treated as an unimplemented instruction,
resulting in a software emulation exception.
The FPECR is a 32-bit supervisor-level internal status and control register used by the
floating-point assist firmware envelope. It contains four status bits indicating whether
the result of the operation is tiny and whether any of three source operands are denor-
malized. In addition, it contains one control bit to enable or disable SIE mode. This reg-
ister must not be accessed by user code.
Table
/
MPC556
REVISION
VERSION
Name
3-17.
Table 3-16 Processor Version Register Bit Descriptions
A 16-bit number that identifies the version of the processor and of the PowerPC architec-
ture. MPC555 / MPC556 value is 0x0002.
A 16-bit number that distinguishes between various releases of a particular version. The
MPC555 / MPC556 value is 0x0020.
Freescale Semiconductor, Inc.
Table 3-17 EIE, EID, AND NRI Registers
SPR Number
(Decimal)
For More Information On This Product,
80
81
82
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
Mnemonic
EID
NRI
EIE
MSR[EE]
Description
1
0
0
Table 3-2
MSR[RI]
1
1
0
and
Table
3-3.
MOTOROLA
3-26