MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 233

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

6.13.2 SIU Interrupt Registers
6.13.2.1 SIPEND Register
6.13.2.2 SIU Interrupt Mask Register (SIMASK)
MPC555
USER’S MANUAL
SIPEND — SIU Interrupt Pending Register
SIMASK — SIU Interrupt Mask Register
IRM0* LVM0
IRQ0
MSB
MSB
16
0
0
0
0
0
RESET:
RESET:
RESET:
The SIU interrupt controller contains the SIPEND, SIMASK, SIEL, and SIVEC regis-
ters.
Each of the 32 bits in the SIPEND register corresponds to an interrupt request. The
bits associated with internal exceptions indicate, if set, that an interrupt service is re-
quested (if not masked by the corresponding bit in the SIMASK register). Each bit re-
flects the status of the internal requestor device and is cleared when the appropriate
actions are initiated by the software in the device itself. Writing to these bits while they
are not set has no effect.
The bits associated with the IRQ pins have a different behavior depending on the sen-
sitivity defined for them in the SIEL register. When the IRQ is defined as a “level” in-
terrupt the corresponding bit behaves similar to the bits associated with internal
interrupt sources. When the IRQ is defined as an “edge” interrupt and if the corre-
sponding bit is set, it indicates that a falling edge was detected on the line and the bit
can be reset by software by writing a 1 to it.
The SIMASK is a 32-bit read/write register. Each bit corresponds to an interrupt re-
quest bit in the SIPEND register. Setting a bit in this register allows the interrupt re-
quest to reach the RCPU. SIMASK is updated by the software and cleared upon reset.
It is the responsibility of the software to determine which of the interrupt sources are
enabled at a given time.
LVL0
17
/
1
0
0
1
0
MPC556
IRQ1
IRM1
18
2
0
0
2
0
LVM1
LVL1
19
3
0
0
3
0
Freescale Semiconductor, Inc.
IRM2
IRQ2
SYSTEM CONFIGURATION AND PROTECTION
20
4
0
0
4
0
For More Information On This Product,
LVM2
LVL2
21
5
0
0
5
0
Go to: www.freescale.com
IRM3
IRQ3
Rev. 15 October 2000
22
6
0
0
6
0
LVM3
LVL3
RESERVED
23
7
0
0
7
0
IRQ4
IRM4
24
8
0
0
8
0
LVM4
LVL4
25
9
0
0
9
0
IRM5
IRQ5
10
26
10
0
0
0
LVM5
LVL5
11
27
11
0
0
0
IRQ6
IRM6
12
28
12
0
0
0
LVM6
LVL6
13
29
13
0
0
0
0x2F C010
0x2F C014
MOTOROLA
IRQ7
IRM7
14
30
14
0
0
0
LVM7
LVL7
LSB
15
31
15
6-25
0
0
0