MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 937

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

G.21 MIOS Timing Characteristics
MPC555 / MPC556
USER’S MANUAL
MCPSM Enable to vs_pclk Pulse
NOTES:
Note 1: f
Note 2: The numbers associated with the f
Note 3: vs_pclk is the MIOS prescaler clock which is distributed around the MIOS to counter modules such as the
1. The MCPSM clock prescaler value (MCPSMSCR_PSL[3:0]) should be written to the MCPSMSCR (MCPSM sta-
2. After reset MCPSMSCR_PSL[3:0] is set to 0b0000.
Prescaler enable
All MIOS output pins are slew rate controlled. Slew rate control circuitry adds 90 ns as
minimum to the output timing and 650 ns as a maximum. This slew rate is from 10%
V
tus/control register) before rewriting the MCPSMSCR to set the enable bit (MCPSMSCR_PREN). If this is not
done the prescaler will start with the old value in the MCPSMSCR_PSL[3:0] before reloading the new value into
the counter.
vs_pclk is the MIOS prescaler clock which is distributed to all the counter (e.g., MPWMSM and MMCSM) submod-
ules.
DDH
MIOB vs_pclk
MMCSM and MPWMSM.
SYS
bit (PREN)
to 90% V
Characteristic
is the internal system clock for the IMB3 bus.
Figure G-34 MCPSM Enable to vs_pclk Pulse Timing Diagram
f
SYS
DDH
, an additional 100 ns should be added for total 0 to V
Table G-21 MCPSM Timing Characteristics
Freescale Semiconductor, Inc.
1
For More Information On This Product,
ELECTRICAL CHARACTERISTICS
Go to: www.freescale.com
SYS
Rev. 15 October 2000
Symbol
t
CPSMC
t
CPSMC
ticks refer to the IMB3 internal state.
(MCPSMSCR_PSL[3:0]) -1
Delay
2
DDH
MOTOROLA
slew rate.
IMB Clock
Cycles
Unit
G-59