MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 714

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
NOTES:
Event Name
masked (ignored) whenever a word is accessed and the least-significant bit is masked
whenever a half-word is accessed. (For more information refer to
Half-Word Working
and less than. These signals are used to generate one of the following four events
(one from each comparator): equal, not equal, greater than, less than.
There are two load/store data comparators (comparators G,H) each is 32 bits wide and
can be programmed to treat numbers either as signed values or as unsigned values.
Each data comparator operates as four independent byte comparators. Each byte
comparator has a mask bit and generates two output signals: equal and less than, if
the mask bit is not set. Therefore, each 32 bit comparator has eight output signals.
These signals are used to generate the “equal and less than” signals according to the
compare size programmed by the user (byte, half-word, word). When operating in byte
mode all signals are significant, when operating in half-word mode only four signals
from each 32 bit comparator are significant. When operating in word mode only two
signals from each 32 bit comparator are significant.
From the new “equal and less than” signals and according to the compare type pro-
grammed by the user one of the following four match events are generated: equal, not
equal, greater than, less than. Therefore, from the two 32-bit comparators eight match
indications are generated: Gmatch[0:3], Hmatch[0:3].
According to the lower bits of the address and the size of the cycle, only match indica-
tions that were detected on bytes that have valid information are validated, the rest are
negated. Note that if the cycle executed has a smaller size than the compare size (e.g.,
a byte access when the compare size is word or half-word) no match indication will be
asserted.
Using the match indication signals four load/store data events are generated in the fol-
lowing way.
The four load/store data events together with the match events of the load/store ad-
dress comparators and the instruction watchpoints are used to generate the load/store
watchpoints and breakpoint according to the users programming.
1. ‘&’ denotes a logical AND, ‘|’ denotes a logical OR
(G | H)
(G&H)
G
H
/
MPC556
(Gmatch0 | Gmatch1 | Gmatch2 | Gmatch3)
(Hmatch0 | Hmatch1 | Hmatch2 | Hmatch3)
((Gmatch0 & Hmatch0) | (Gmatch1 & Hmatch1) | (Gmatch2 & Hmatch2) | (Gmatch3 & Hmatch3))
((Gmatch0 | Hmatch0) | (Gmatch1 | Hmatch1) | (Gmatch2 | Hmatch2) | (Gmatch3 | Hmatch3))
Freescale Semiconductor, Inc.
Modes). Each comparator generates two output signals: equal
For More Information On This Product,
Table 21-7 Load/Store Data Events
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
Event Function
1
21.3.1.2 Byte and
MOTOROLA
21-18