MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 499

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.7.5.7 Master Wraparound Mode
14.7.6 Slave Mode
MPC555
USER’S MANUAL
To configure a peripheral chip select, set the appropriate bit in PQSPAR, then config-
ure the chip-select pin as an output by setting the appropriate bit in DDRQS. The value
of the bit in PORTQS that corresponds to the chip-select pin determines the base state
of the chip-select signal. If the base state is zero, chip-select assertion must be active
high (PCS bit in command RAM must be set); if base state is one, assertion must be
active low (PCS bit in command RAM must be cleared). PORTQS bits are cleared dur-
ing reset. If no new data is written to PORTQS before pin assignment and configura-
tion as an output, the base state of chip-select signals is zero and chip-select pins are
configured for active-high operation.
Wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap
to pointer address 0x0 or to the address pointed to by NEWQP, depending on the state
of the WRTO bit in SPCR2.
In wraparound mode, the QSPI cycles through the queue continuously, even while the
QSPI is requesting interrupt service. SPE is not cleared when the last command in the
queue is executed. New receive data overwrites previously received data in receive
RAM. Each time the end of the queue is reached, the SPIF flag is set. SPIF is not au-
tomatically reset. If interrupt-driven QSPI service is used, the service routine must
clear the SPIF bit to end the current interrupt request. Additional interrupt requests dur-
ing servicing can be prevented by clearing SPIFIE, but SPIFIE is buffered. Clearing it
does not end the current request.
Wraparound mode is exited by clearing the WREN bit or by setting the HALT bit in
SPCR3. Exiting wraparound mode by clearing SPE is not recommended, as clearing
SPE may abort a serial transfer in progress. The QSPI sets SPIF, clears SPE, and
stops the first time it reaches the end of the queue after WREN is cleared. After HALT
is set, the QSPI finishes the current transfer, then stops executing commands. After
the QSPI stops, SPE can be cleared.
Clearing the MSTR bit in SPCR0 selects slave mode operation. In slave mode, the
QSPI is unable to initiate serial transfers. Transfers are initiated by an external SPI bus
master. Slave mode is typically used on a multi-master SPI bus. Only one device can
be bus master (operate in master mode) at any given time.
Before QSPI operation is initiated, QSMCM register PQSPAR must be written to as-
sign necessary pins to the QSPI. The pins necessary for slave mode operation are MI-
SO, MOSI, SCK, and PCS[0]/SS. MISO is used for serial data output in slave mode,
and MOSI is used for serial data input. Either or both may be necessary, depending
on the particular application. SCK is the serial clock input in slave mode and must be
assigned to the QSPI for proper operation. Assertion of the active-low slave select sig-
nal SS initiates slave mode operation.
Before slave mode operation is initiated, DDRQS must be written to direct data flow
on the QSPI pins used. Configure the MOSI, SCK and PCS[0]/SS pins as inputs. The
MISO pin must be configured as an output.
/
MPC556
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
14-37