MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 276

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

8.8.2 Power Mode Descriptions
8.8.3 Exiting from Low-Power Modes
MPC555
USER’S MANUAL
Table 8-5
for each power mode.
Exiting from low-power modes occurs through an asynchronous interrupt or a synchro-
nous interrupt generated by the memory controller. Any enabled asynchronous inter-
rupt clears the LPM bits but does not change the PLPRCR[CSRC] bit.
The exit from normal-low, doze-high, and low modes and sleep mode to normal-high
mode is accomplished with the asynchronous interrupt. The sources of the asynchro-
nous interrupt are:
The system response to asynchronous interrupts is fast. The wake-up time from nor-
mal-low, doze-high, doze-low, and sleep mode due to an asynchronous interrupt or
• Asynchronous wake-up interrupt from the interrupt controller
• RTC, PIT, or time base interrupts (if enabled)
• Decrementer exception
/
MPC556
Normal-low (“gear”)
describes the power consumption, clock frequency, and chip functionality
Operation Mode
Power-down
Normal-high
Deep-sleep
VDDSRAM
Doze-high
Doze-low
Table 8-4 Power Mode Control Bit Descriptions
Sleep
Freescale Semiconductor, Inc.
Normal-low (“gear”)
Table 8-5 Power Mode Descriptions
For More Information On This Product,
Power Mode
Power-down
Normal-high
Deep-sleep
Doze-high
Doze-low
Sleep
CLOCKS AND POWER CONTROL
Not active
Not active
Not active
Active
Active
Active
Active
Active
SPLL
Go to: www.freescale.com
Rev. 15 October 2000
LPM[0:1]
Full frequency ÷
Full frequency ÷
Full frequency ÷
Full frequency ÷
00
00
01
01
10
11
11
Not active
Not active
Not active
Not active
2
2
Clocks
2
2
DFNL+1
DFNL+1
DFNH
DFNH
CSRC
X
X
X
0
1
0
1
Full functions not in use
Enabled: RTC, PIT, TB
Enabled: RTC, PIT,
Disabled: extended
(RCPU, BBC, FPU)
memory controller
TEXPS
Functionality
TB and DEC,
SRAM’s data
X
X
X
X
X
1
0
are shut off
and DEC
retention
core
MOTOROLA
8-16