MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 242

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

6.13.4.8 Periodic Interrupt Status and Control Register (PISCR)
6.13.4.9 Periodic Interrupt Timer Count Register (PITC)
MPC555
USER’S MANUAL
PISCR — Periodic Interrupt Status and Control Register
PITC — Periodic Interrupt Timer Count
HARD RESET:
Bit(s)
MSB
MSB
9:12
0:7
16
13
14
15
0
0
0
0
0
8
RESET:
RESET:
The PISCR contains the interrupt request level and the interrupt status bit. It also con-
tains the controls for the 16 bits to be loaded into a modulus counter. This register can
be read or written at any time.
The PITC register contains the 16 bits to be loaded in a modulus counter. This register
is readable and writable at any time.
17
/
1
0
1
0
0
MPC556
Name
PIRQ
PITF
PTE
PIE
PS
—
18
2
0
2
0
0
Periodic interrupt request. These bits determine the interrupt priority level of the PIT. Refer to
Interrupt Controller
Periodic interrupt status. This bit is set if the PIT issues an interrupt. The PIT issues an interrupt
after the modulus counter counts to zero. PS can be negated by writing a one to it. A write of zero
has no affect.
Reserved
Periodic interrupt enable. If this bit is set, the time base generates an interrupt when the PS bit
is set.
PIT freeze. If this bit is set, the PIT stops while FREEZE is asserted.
Periodic timer enable
0 = PIT stops counting and maintains current value
1 = PIT continues to decrement
19
3
0
3
0
0
PIRQ
Freescale Semiconductor, Inc.
SYSTEM CONFIGURATION AND PROTECTION
20
4
0
4
0
0
For More Information On This Product,
Table 6-18 PISCR Bit Descriptions
21
5
0
5
0
0
Go to: www.freescale.com
for interrupt level encodings.
Rev. 15 October 2000
22
6
0
6
0
0
RESERVED
23
7
0
7
0
0
PITC
PS
24
8
0
8
0
0
Description
25
9
0
9
0
0
RESERVED
10
10
26
0
0
0
11
11
27
0
0
0
12
12
28
0
0
0
PIE
13
13
29
0
0
0
0x2F C240
0x2F C244
MOTOROLA
PITF
14
14
30
0
0
0
LSB
PTE
LSB
15
15
31
6-34
0
0
0
6.4