MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 214

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

6.2.2 Address Decoding for External Accesses
6.3 USIU General-Purpose I/O
MPC555
USER’S MANUAL
The external master may access the internal MPC555 / MPC556 special registers that
are located outside the RCPU. In order to access one of these MPC555 / MPC556 reg-
isters, program the EMCR to MPC555 / MPC556 special register access (CONT = 1
and SUPU = 0 in EMCR). Next, access the register by providing the address according
to the MPC555 / MPC556 address map. Only the first external master access that fol-
lows EMCR setting will be assigned to the special register map; the next accesses will
be directed to the normal address map. This is done in order to enable the user to ac-
cess the EMCR again after the required MPC555 / MPC556 special register access.
Peripheral mode does not require external bus arbitration between the external master
and the internal RCPU, since the internal RCPU is disabled. The BR and BB signals
should be connected to ground, and the internal bus arbitration should be selected in
order to prevent the “slave” MPC555 / MPC556 from occupying the external bus. In-
ternal bus arbitration is selected by clearing the EARB bit in the SIUMCR (see
SIU Module Configuration
During an external master access, the USIU compares the external address with the
internal address block to determine if MPC555 / MPC556 operation is required. Since
only 24 of the 32 internal address bits are available on the external bus, the USIU as-
signs zeros to the most significant address bits (ADDR[0:7]).
The address compare sequence can be summarized as follows:
When trying to fetch an MPC555 / MPC556 special register from an external master,
the address might be aliased to one of the external devices on the external bus. If this
device is selected by the MPC555 / MPC556 internal memory controller, this aliasing
does not occur since the chip select is disabled. If the device has its own address de-
coding or is being selected by external logic, this case should be resolved.
The USIU provides 64 general-purpose I/O (SGPIO) pins. The SGPIO pins are multi-
plexed with the address and data pins. In single-chip mode, where communicating with
external devices is not required, the user can use all 64 SGPIO pins. In multiple-chip
mode, only eight SGPIO pins are available. Another configuration allows the use of the
address bus for instruction show cycles while the data bus is dedicated to SGPIO func-
• Normal external access. If the CONT bit in EMCR is cleared, the address is com-
• MPC555 / MPC556 special register external access. If the CONT bit in EMCR is
• Memory controller external access. If the first two comparisons do not match, the
/
pared to the internal address map.
set by the previous external master access, the address is compared to the
MPC555 / MPC556 special address range. See
Map
internal memory controller determines whether the address matches an address
assigned to one of the regions. If it finds a match, the memory controller gener-
ates the appropriate chip select and attribute accordingly
MPC556
for a list of the SPRs in the USIU.
Freescale Semiconductor, Inc.
SYSTEM CONFIGURATION AND PROTECTION
For More Information On This Product,
Register).
Go to: www.freescale.com
Rev. 15 October 2000
5.4 USIU PowerPC Memory
MOTOROLA
6.13.1.1
6-6