MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 407

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Table 12-4
multiplexing. In this case the ILBS lines remain at 00 at all times, as shown in
12-4. In this mode, no interrupts from IMB modules which assert on levels 8 through
31 are ever latched by the Interrupt synchronizer. Time multiplexing is disabled during
reset, but the reset default value enables time multiplexing as soon as reset is re-
leased if the reset default value is not 00.
The timing for the scheme and the values of ILBS and the interrupt levels driven onto
the IMB IRQ lines are shown in
of four clocks and an average latency of two clocks before the interrupt request can
reach the interrupt synchronizer.
The IRQMUX bits determine how many levels of IMB interrupts are sampled. Refer to
Table
IRQMUX[0:1]
ILBS [0:1]
IMB CLOCK
IMB LVL[0:7]]
/
00
01
10
11
MPC556
12-4.
shows ILBS sequencing. Programming IRQMUX[0:1] to 00 disables time
Figure 12-5 Time-Multiplexing Protocol for IRQ pins
00, 00, 00.....
00, 01, 00, 01....
00, 01, 10, 00, 01, 10,.....
00, 01, 10, 11, 00, 01, 10, 11,....
ILBS[0:1]
00
01
10
11
Freescale Semiconductor, Inc.
00
Table 12-3 ILBS Signal functionality
For More Information On This Product,
U-BUS TO IMB3 BUS INTERFACE (UIMB)
Table 12-4 IRQMUX Functionality
ILBS sequence
IMB interrupt sources mapped onto 0:7 levels will
drive interrupts onto IMB IRQ[0:7]
IMB interrupt sources mapped onto 8:15 levels will
drive interrupts onto IMB IRQ[0:7]
IMB interrupt sources mapped onto 16:23 levels will
drive interrupts onto IMB IRQ[0:7]
IMB interrupt sources mapped onto 24:31 levels will
drive interrupts onto IMB IRQ[0:7]
01
LVL
0:7
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Rev. 15 October 2000
Figure
10
LVL
8:15
12-5. This scheme causes a maximum latency
.
16:23
11
LVL
Description
Latch 0:7 IMB interrupt levels
Latch 0:15 IMB interrupt levels
Latch 0:23 IMB interrupt levels
Latch 0:31 IMB interrupt levels
24:31
00
LVL
01
LVL
0:7
Description
10
11
MOTOROLA
Table
12-5