MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 724

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
• NMI exception as a result of the assertion of the IRQ0_B pin. For more information
• Check stop. Refer to
• Machine check exception
• Implementation specific instruction protection error
• Implementation specific data protection error
• External interrupt, recognized when MSREE = 1
• Alignment interrupt
• Program interrupt
• Floating point unavailable exception
• Floating point assist exception
• Decrementer exception, recognized when MSREE = 1
• System call exception
• Trace, asserted when in single trace mode or when in branch trace mode (refer to
• Implementation dependent software emulation exception
• Instruction breakpoint, when breakpoints are masked (BRKNOMSK bit in the
• Load/store breakpoint, when breakpoints are masked (BRKNOMSK bit in the
• Peripherals breakpoint, from the development port, internal and external modules.
• Development port non-maskable interrupt, as a result of a debug station request.
The internal freeze signal is asserted whenever an enabled event occurs, regardless
if debug mode is enabled or disabled. The internal freeze signal is connected to all rel-
evant internal modules. These modules can be programmed to stop all operations in
response to the assertion of the freeze signal. Refer to
The freeze indication is negated when exiting debug mode. Refer to
Debug Mode
The following list contains the events that can cause the CPU to enter debug mode.
Each event results in debug mode entry if debug mode is enabled and the correspond-
ing enable bit is set. The reset values of the enable bits let the user, in most cases, to
use of the debug mode features without the need to program the debug enable register
(DER). For more information refer to
refer to
3.15.4.10 Trace
LCTRL2 is clear) recognized only when MSRRI = 1, when breakpoints are not
masked (BRKNOMSK bit in the LCTRL2 is set) always recognized
LCTRL2 is cleared) recognized only when MSRRI = 1, when breakpoints are not
masked (BRKNOMSK bit in the LCTRL2 is set) always recognized
are recognized only when MSRRI = 1.
Useful in some catastrophic events like an endless loop when MSRRI = 0. As a result
of this event the machine may enter a non-restartable state, for more information re-
fer to
/
MPC556
3.15.4
3.15.4.1 System Reset Interrupt
Interrupts.
Interrupt)
Freescale Semiconductor, Inc.
For More Information On This Product,
21.4.1.3 The Check Stop State and Debug Mode
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
21.7.12 Debug Enable Register
21.6.1 Freeze
21.4.1.6 Exiting
Indication.
(DER).
MOTOROLA
21-28