MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 729

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.5.6.1 Development Port Shift Register
21.5.6.2 Trap Enable Control Register
21.5.6.3 Development Port Registers Decode
MPC555
USER’S MANUAL
formed. It is also used as a temporary holding register for data to be stored into the
TECR. These registers are discussed below in more detail.
The development port shift register is a 35-bit shift register. Instructions and data are
shifted into it serially from DSDI using DSCK (or CLKOUT depending on the debug
port clock mode, refer to
Clock Mode Selection
ferred in parallel to the CPU, the trap enable control register (TECR). When the pro-
cessor enters debug mode it fetches instructions from the DPIR which causes an
access to the development port shift register. These instructions are serially loaded
into the shift register from DSDI using DSCK (or CLKOUT) as the shift clock. In a sim-
ilar way, data is transferred to the CPU by moving it into the shift register which the
processor reads as the result of executing a “move from special purpose register DP-
DR” instruction. Data is also parallel-loaded into the development port shift register
from the CPU by executing a “move to special purpose register DPDR” instruction. It
is then shifted out serially to DSDO using DSCK (or CLKOUT) as the shift clock.
The trap enable control register is a 9-bit register that is loaded from the development
port shift register. The contents of the control register are used to drive the six trap en-
able signals, the two breakpoint signals, and the VSYNC signal to the CPU. The
“transfer data to trap enable control register” commands will cause the appropriate bits
to be transferred to the control register.
The trap enable control register is not accessed by the CPU, but instead supplies sig-
nals to the CPU. The trap enable bits, VSYNC bit, and the breakpoint bits of this reg-
ister are loaded from the development port shift register as the result of trap enable
mode transmissions. The trap enable bits are reflected in ICTRL and LCTRL2 special
registers. See
Control Register
The development port shift register is selected when the CPU accesses DPIR or DP-
DR. Accesses to these two special purpose registers occur in debug mode and appear
on the internal bus as an address and the assertion of an address attribute signal in-
dicating that a special purpose register is being accessed. The DPIR register is read
by the CPU to fetch all instructions when in debug mode and the DPDR register is read
and written to transfer data between the CPU and external development tools. The
DPIR and DPDR are pseudo registers. Decoding either of these registers will cause
the development port shift register to be accessed. The debug mode logic knows
whether the CPU is fetching instructions or reading or writing data. If what the CPU is
expecting and what the register receives from the serial port do not match (instruction
instead of data) the mismatch is used to signal a sequence error to the external devel-
opment tool.
/
MPC556
21.7.6 I-Bus Support Control Register
2.
Freescale Semiconductor, Inc.
For More Information On This Product,
)
as the shift clock. These instructions or data are then trans-
21.5.6.4 Development Port Serial Communications —
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
and
21.7.8 L-Bus Support
MOTOROLA
21-33