MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 668

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

19.3.1 Address Range of Shadow Information
19.3.2 Reset Configuration Word (CMFCFIG)
MPC555
USER’S MANUAL
The address range of the shadow information is the entire address range of the CMF
EEPROM array but the high order array addresses, ADDR[14:23], are not used to en-
code the location. The first 16 bytes (ADDR[24:29] = 0x00 to 0x0F) of the 256 bytes of
shadow locations are withheld by Motorola for the reset configuration word and future
applications. The remaining 240 bytes are available as supervisor data. This is shown
in
The CMF EEPROM reset configuration word is implemented in the first word (AD-
DR[24:29] = 0x00) of the special shadow locations. The reset configuration word along
with the rest of the shadow information words is located in supervisor data address
space. The purpose of the reset configuration word is to provide the system with an
alternative internal source for the reset configuration.
Note that with the exception of bit 20, the bits in the CMFCFIG are identical to those
in the USIU hard reset configuration word. Refer to
Word
Figure
/
MPC556
for descriptions of these bits.
19-2.
When SIE = 1, only program page buffer zero can be programmed.
All programming writes to the CMF will be directed to program page
buffer 0 if SIE = 1. In addition, the other program page buffers cannot
be accessed and will not apply any programming voltages to their
CMF array blocks while programming the shadow information.
0xFF
0x0F
0x00
0x03
0x04
0x10
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 19-2 Shadow Information
General-Use MoneT Shadow Information
CDR MoneT FLASH EEPROM
Reserved for Future Applications
Go to: www.freescale.com
Rev. 15 October 2000
Reset Configuration Word
NOTE
7.5.2 Hard Reset Configuration
MOTOROLA
19-16