MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 328

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.5.6.2 Bus Grant
9.5.6.3 Bus Busy
MPC555
USER’S MANUAL
The arbiter asserts BG to indicate that the bus is granted to the requesting device. This
signal can be negated following the negation of BR or kept asserted for the current
master to park the bus.
When configured for external central arbitration, BG is an input signal to the MPC555
/ MPC556 from the external arbiter. When the internal on-chip arbiter is used, this sig-
nal is an output from the internal arbiter to the external bus master.
BB assertion indicates that the current bus master is using the bus. New masters
should not begin transfer until this signal is negated. The bus owner should not relin-
quish or negate this signal until the transfer is complete. To avoid contention on the
BB line, the master should three-state this signal when it gets a logical one value. This
requires the connection of an external pull-up resistor to ensure that a master that ac-
quires the bus is able to recognize the BB line negated, regardless of how many cycles
have passed since the previous master relinquished the bus. Refer to
/
MPC556
MPC555
Figure 9-24 Masters Signals Basic Connection
Freescale Semiconductor, Inc.
For More Information On This Product,
EXTERNAL BUS INTERFACE
Go to: www.freescale.com
Rev. 15 October 2000
External Bus
TS
BB
Slave 2
Figure
MOTOROLA
Master
9-24.
9-32