MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 678

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

19.6.2 Erase Margin Reads
19.6.3 Erasing Shadow Information Words
MPC555
USER’S MANUAL
State
S1
S2
S3
S4
S5
The CMF EEPROM provides an erase margin read with electrical margin for the erase
state. Erase margin reads provide sufficient margin to ensure specified data retention.
The erase margin read is enabled when SES = 1 and the erase write has occurred.
The erase margin read and subsequent on-page erase verify reads return a zero for
any bit that has not been completely erased. Bits that have completed erasing return
one when read. To increase the access time of the erase margin read, the off-page
access time is 16 clocks instead of the usual two clock off-page read access time. The
erase margin read occurs during an off-page read. All locations within the block(s) be-
ing erased must return one when read to determine that no more erase pulses are re-
quired.
The shadow information words are erased with CMF array block zero. To verify that
the shadow information words are erased, the SIE bit in CMFMCR must be set to one
Normal Operation:
Normal array reads and register accesses. The
Block protect information and pulse width timing
control can be modified.
Erase Hardware Interlock Write:
Normal read operation still occurs. The CMF ac-
cepts the erase hardware interlock write. This write
may be to any CMF array location. Accesses to the
registers are normal register accesses. A write to
CMFCTL can not set EHV at this time. A write to
the register is not an erase hardware interlock
write, and the CMF remains in state S2.
High Voltage Write Enable
Erase margin reads will occur. Accesses to the
registers are normal register accesses. A write to
CMFCTL can change EHV.
Erase Operation:
High voltage is applied to the array blocks to erase
the CMF bit cells. The pulse width timer is active if
SCLKR[0:2] ≠ 0, and HVS can be polled to time the
erase pulse. During the erase operation, the array
does not respond to any address. Accesses to the
registers are allowed. A write to CMFCTL can
change EHV only.
Erase Margin Read Operation:
These reads determine whether the state of the
bits in the selected blocks needs further modifica-
tion by the erase operation. Once a bit is fully
erased it returns one when read. All words within
the blocks being erased must be read to determine
whether the erase operation is completed.
/
MPC556
Table 19-11 Erase Interlock State Descriptions
Freescale Semiconductor, Inc.
Mode
For More Information On This Product,
CDR MoneT FLASH EEPROM
Go to: www.freescale.com
Rev. 15 October 2000
State
Next
S2
S1
S3
S1
S4
S1
S5
S4
S1
T2
T1
T3
T6
T4
T7
T5
T8
T9
A successful write to any CMF array lo-
cation is the erase interlock write. If the
ware interlock write has not been done
and the CMF will remain in state S2.
write is to a register the erase hard-
Write EHV = 0, disable the internal
Write SES = 0 or a master reset
Write SES = 0 or a master reset
Write SES = 0 or a master reset
Transition Requirement
memory map or a soft reset
Write PE = 1, SES = 1.
Hardware Interlock
Write EHV = 1
Write EHV=1
Master reset
MOTOROLA
19-26