MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 663

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

19.2.2 CMF EEPROM Array Addressing
MPC555
USER’S MANUAL
Bit(s)
27:28
26
29
30
31
The CMF EEPROM array is addressed when an internal access has been initialized
and ADDR[10:13] matches the array hardware mapping address. The CMF array lo-
cation selected is determined by ADDR[14:29] and the bytes are selected by AD-
DR[30:31] and internal SIZE[0:1] information.
internal mapping of the flash array.
Information in the array is accessed in 32-byte pages. For each CMF module, two read
page buffers are assigned to the low order addresses (ADDR[27:31]). The first page
buffer is assigned to blocks zero to three; the second to blocks four to seven (for CMF
Module A) or four to five (for CMF Module B).
Access time for data in the read page buffers is one system clock; access time for an
off-page read is two system clocks. To prevent the BIU from accessing an unneces-
sary page from the array, the CMF EEPROM monitors the U-bus address to determine
whether the required information is within one of the two read page buffers and the ac-
cess is valid for the module. This strategy allows the CMF EEPROM to have a two-
clock read for an off-page access and one clock for an on-page access.
The BIU does not recognize write accesses to the CMF array.
/
MPC556
Name
EPEE
SES
EHV
PE
—
EPEE pin status bit. The EPEE bit monitors the state of the external program/erase enable
(EPEE) pin. EPEE has a digital filter that requires two consecutive samples to be equal before
the output of the filter changes. The CMF samples EPEE when EHV is asserted and holds the
EPEE state until EHV is negated. EPEE is a read-only bit; writes have no effect.
0 = High voltage operations are not possible
1 = High voltage operations are possible
Refer to
Reserved
Program or erase select. PE configures the CMF EEPROM for programming or erasing. When
PE = 0, the array is configured for programming and if SES = 1 the SIE bit will be write locked.
When PE = 1, the array is configured for erasing and SES will not write lock the SIE bit.
The PE bit is write protected by the SES bit. Writes to CMFCTL will not change PE if SES = 1.
0 = Configure for program operation (default value)
1 = Configure for erase operation
Start-end program or erase sequence. The SES bit is write protected by the HVS and EHV bits,
unless the PAW bits are set to 0b1xx. Writes to CMFCTL will not change SES if HVS = 1 or EHV
= 1. Refer to
0 = CMF EEPROM not configured for program or erase operation
1 = Configure CMF EEPROM for program or erase operation
Enable high voltage. EHV can be asserted only after the SES bit has been asserted and a valid
programming write(s) or erase hardware interlock write has occurred. If an attempt is made to
assert EHV when SES is negated, or if a valid programming write(s) or erase hardware interlock
write has not occurred since SES was asserted, EHV will remain negated.
0 = Program or erase pulse disabled
1 = Program or erase pulse enabled
Table 19-6 CMFCTL Bit Descriptions (Continued)
Freescale Semiconductor, Inc.
19.9.1 E
For More Information On This Product,
19.7.7 Starting and Ending a Program or Erase Sequence
PEE
CDR MoneT FLASH EEPROM
Go to: www.freescale.com
Signal
Rev. 15 October 2000
for more information.
Description
Table 19-6
and
Table 19-7
for more information.
MOTOROLA
show the
19-11