MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 623

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

17.3.7 TPU3 Interrupts
17.3.8 Prescaler Control for TCR1
MPC555
USER’S MANUAL
TPU function library. Refer to the Motorola
for more information about specific functions.
Each of the TPU3 channels can generate an interrupt service request. Interrupts for
each channel must be enabled by writing to the appropriate control bit in the channel
interrupt enable register (CIER). The channel interrupt status register (CISR) contains
one interrupt status flag per channel. Time functions set the flags. Setting a flag bit
causes the TPU3 to make an interrupt service request if the corresponding channel
interrupt enable bit is set.
The TPU3 can generate one of 32 possible interrupt request levels on the IMB3. The
value driven onto IRQ[7:0] represents the interrupt level programmed in the IRL field
of the TPU interrupt configuration register (TICR). Under the control of the ILBS bits in
the ICR, each interrupt request level is driven during the time multiplexed bus during
one of four different time slots, with eight levels communicated per time slot. No hard-
ware priority is assigned to interrupts. Furthermore, if more than one source on a mod-
ule requests an interrupt at the same level, the system software must assign a priority
to each source requesting at that level.
scheme.
Timer count register 1 (TCR1) is clocked from the output of a prescaler. The following
fields control TCR1:
The rate at which TCR1 is incremented is determined as follows:
ILBS[1:0]
IMB3 CLOCK
IMB3 IRQ[7:0]
• The PSCK and TCR1P fields in TPUMCR
• The DIV2 field in TPUMCR2
• The EPSCKE and EPSCK fields in TPUMCR3.
• The user selects either the standard prescaler (by clearing the enhanced prescal-
/
er enable bit, EPSCKE, in TPUMCR3) or the enhanced prescaler (by setting
EPSCKE).
MPC556
Freescale Semiconductor, Inc.
00
For More Information On This Product,
Figure 17-2 TPU3 Interrupt Levels
01
IRQ
7:0
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
Rev. 15 October 2000
10
IRQ
15:8
23:16
11
IRQ
TPU Literature Package (TPULITPAK/D)
Figure 17-2
31:24
00
IRQ
01
IRQ
7:0
displays the interrupt level
10
11
MOTOROLA
17-5