MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 273

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

8.7 Clock Source Switching
MPC555
USER’S MANUAL
When the PLL is acquiring lock, the ENGCLK signal is disabled and remains in the low
state (provided that BUCS = 0).
For limp mode support, clock source switching is supported. If for any reason the clock
source for the chip is not functioning, the user has the option to switch the system clock
to the backup clock ring oscillator, BUCLK.
This circuit consists of a loss-of-clock detector, which sets the LOCS status bit and
LOCSS sticky bit in the PLPRCR. If the LME bit in the SCCR is set, whenever LOCS
is asserted the clock logic switches the system clock automatically to BUCLK and as-
serts hard reset to the chip. Switching the system clock to BUCLK is also possible by
software setting the STBUC bit in SCCR. Switching from limp mode to normal system
operation is accomplished by clearing STBUC and LOCSS bits. This operation also
asserts hard reset to the chip.
At HRESET assertion, if the PLL output clock is not valid, the BUCLK will be selected
until software clears LOCSS bit in SCCR. At HRESET assertion, if the PLL output
clock is valid, the system will switch to oscillator/external clock. If during HRESET the
PLL loses lock or the clock frequency becomes slower than the required value, the
system will switch to the BUCLK. After HRESET negation, the PLL lock condition does
not effect the system clock source selection.
If the LME bit is clear, the switch to the backup clock is disabled and assertion of ST-
BUC bit is ignored. If the chip is in limp mode, clearing the LME bit switches the system
to normal operation and asserts hard reset to the chip.
Figure 8-8
tus and control for each state.
/
MPC556
Skew elimination between CLKOUT and ENGCLK is not guaranteed.
describes the clock switching control logic.
Freescale Semiconductor, Inc.
For More Information On This Product,
CLOCKS AND POWER CONTROL
Go to: www.freescale.com
Rev. 15 October 2000
NOTE
Table 8-3
summarizes the sta-
MOTOROLA
8-13