MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 434

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
lected. By programming the MQ1(2) field in QACR1(2), the following software initiated
modes can be selected:
When a queue is programmed for a continuous-scan mode, the single-scan enable bit
in the queue control register does not have any meaning or effect. As soon as the
queue operating mode is programmed, the selected trigger event can initiate queue
execution.
In the case of the software initiated continuous-scan mode, the trigger event is gener-
ated internally and queue execution begins immediately. In the other continuous-scan
queue operating modes, the selected trigger event must occur before the queue can
start. A trigger overrun is captured if a trigger event occurs during queue execution in
the external trigger continuous-scan mode and the periodic timer continuous-scan
mode.
After the queue execution is complete, the queue status is shown as idle. Since the
continuous-scan queue operating modes allow the entire queue to be scanned multi-
ple times, software involvement is not needed to enable queue execution to continue
from the idle state. The next trigger event causes queue execution to begin again,
starting with the first CCW in the queue.
Software Initiated Continuous-Scan Mode. When the software initiated continuous-
scan mode is programmed, the trigger event is generated automatically by the
QADC64. Queue execution begins immediately. If a pause is encountered, another
trigger event is generated internally, and then execution continues without pausing.
When the end-of-queue is reached, another internal trigger event is generated, and
queue execution begins again from the beginning of the queue.
While the time to internally generate and act on a trigger event is very short, software
can momentarily read the status conditions, indicating that the queue is idle. The trig-
ger overrun flag is never set while in the software initiated continuous-scan mode.
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
• Software initiated continuous-scan mode
• External trigger continuous-scan mode
• External gated continuous-scan mode (queue 1 only)
• Interval timer continuous-scan mode
In this version of QADC64, coherent samples can be guaranteed.
The time between consecutive conversions has been designed to be
consistent, provided the sample time bits in both the CCW and IST
are identical. However, there is one exception. For queues that end
with a CCW containing EOQ code (channel 63), the last queue con-
version to the first queue conversion requires one additional CCW
fetch cycle. Therefore continuous samples are not coherent at this
boundary.
In addition, the time from trigger to first conversion can not be guar-
anteed since it is a function of clock synchronization, programmable
trigger events, queue priorities, and so on.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
NOTE
MOTOROLA
13-22