MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 137

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

3.7.4 Condition Register (CR)
MPC555
USER’S MANUAL
30–31
Bit(s)
21
22
23
24
25
26
27
28
29
Table 3-6
The condition register (CR) is a 32-bit register that reflects the result of certain opera-
tions and provides a mechanism for testing and branching. The bits in the CR are
grouped into eight 4-bit fields, CR0 to CR7.
VXSQRT
/
VXSOFT
VXCVI
Name
MPC556
OE
RN
VE
UE
XE
ZE
NI
illustrates the floating-point result flags that correspond to FPSCR[15:19].
Floating-point invalid operation exception for software request. This bit can be altered only by the
mcrfs, mtfsfi, mtfsf, mtfsb0, or mtfsb1 instructions. The purpose of VXSOFT is to allow soft-
ware to cause an invalid operation condition for a condition that is not necessarily associated with
the execution of a floating-point instruction. For example, it might be set by a program that com-
putes a square root if the source operand is negative. This is a sticky bit.
Floating-point invalid operation exception for invalid square root. This is a sticky bit. This guar-
antees that software can simulate fsqrt and frsqrte, and to provide a consistent interface to han-
dle exceptions caused by square-root operations.
Floating-point invalid operation exception for invalid integer convert. This is a sticky bit.
Floating-point invalid operation exception enable.
Floating-point overflow exception enable.
Floating-point underflow exception enable. This bit should not be used to determine whether de-
normalization should be performed on floating-point stores.
Floating-point zero divide exception enable.
Floating-point inexact exception enable.
Non-IEEE mode bit.
Floating-point rounding control.
00Round to nearest
01Round toward zero
10Round toward +infinity
11Round toward -infinity
Table 3-6 Floating-Point Result Flags in FPSCR
Table 3-5 FPSCR Bit Descriptions (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
Result Flags
(Bits 15–19)
C<>=?
10001
01001
01000
11000
10010
00010
10100
00100
00101
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Rev. 15 October 2000
+ Denormalized number
– Denormalized number
– Normalized number
+ Normalized number
Result value class
Quiet NaN
Description
– Infinity
+ Infinity
– Zero
+ Zero
MOTOROLA
3-15