MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 737

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.5.6.10 Serial Data Out of Development Port
21.5.6.11 Fast Download Procedure
MPC555
USER’S MANUAL
The encoding of data shifted out of the development port shift register in debug mode
(through the DSDO pin) is the same as for trap enable mode and is shown in
21-12.
Valid data encoding is used when data has been transferred from the CPU to the de-
velopment port shift register. This is the result of an instruction to move the contents
of a general purpose register to the debug port data register (DPDR). The valid data
encoding has the highest priority of all status outputs and will be reported even if an
interrupt occurs at the same time. Since it is not possible for a sequencing error to oc-
cur and also have valid data there is no priority conflict with the sequencing error sta-
tus. Also, any interrupt that is recognized at the same time that there is valid data is
not related to the execution of an instruction. Therefore, a valid data status will be out-
put and the interrupt status will be saved for the next transmission.
The sequencing error encoding indicates that the inputs from the external develop-
ment tool are not what the development port and/or the CPU was expecting. Two cas-
es could cause this error:
This bus error will cause the CPU to signal that an interrupt (exception) occurred.
Since a status of sequencing error has a higher priority than exception, the port will
report the sequencing error first, and the CPU interrupt on the next transmission. The
development port will ignore the command, instruction, or data shifted in while the se-
quencing error or CPU interrupt is shifted out. The next transmission after all error sta-
tus is reported to the port should be a new instruction, trap enable or command
(possibly the one that was in progress when the sequencing error occurred).
The interrupt-occurred encoding is used to indicate that the CPU encountered an in-
terrupt during the execution of the previous instruction in debug mode. Interrupts may
occur as the result of instruction execution (such as unimplemented opcode or arith-
metic error), because of a memory access fault, or from an unmasked external inter-
rupt. When an interrupt occurs the development port will ignore the command,
instruction, or data shifted in while the interrupt encoding was shifting out. The next
transmission to the port should be a new instruction, trap enable or debug port com-
mand.
Finally, the null encoding is used to indicate that no data has been transferred from the
CPU to the development port shift register.
The download procedure is used to download a block of data from the debug tool into
system memory. This procedure can be accomplished by repeating the following se-
quence of transactions from the development tool to the debug port for the number of
data words to be down loaded:
1. The processor was trying to read instructions and there was data shifted into
2. The processor was trying to read data and there was instruction shifted into the
/
MPC556
the development port, or
development port. The port will terminate the read cycle with a bus error.
Freescale Semiconductor, Inc.
For More Information On This Product,
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
Table
21-41