MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 615

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Bit(s)
10:11
0:1
12
13
2
3
4
5
6
7
8
9
/
FORMERR
MPC556
STUFERR
RXWARN
CRCERR
TXWARN
BOFFINT
ACKERR
BITERR
TX/RX
Name
IDLE
FCS
—
Transmit bit error. The BITERR[1:0] field is used to indicate when a transmit bit error occurs.
Refer to
NOTE: The transmit bit error field is not modified during the arbitration field or the ACK slot
bit time of a message, or by a transmitter that detects dominant bits while sending a passive
error frame.
Acknowledge error. The ACKERR bit indicates whether an acknowledgment has been cor-
rectly received for a transmitted message.
0 = No ACK error was detected since the last read of this register
1 = An ACK error was detected since the last read of this register
Cyclic redundancy check error. The CRCERR bit indicates whether or not the CRC of the
last transmitted or received message was valid.
0 = No CRC error was detected since the last read of this register
1 = A CRC error was detected since the last read of this register
Message format error. The FORMERR bit indicates whether or not the message format of
the last transmitted or received message was correct.
0 = No format error was detected since the last read of this register
1 = A format error was detected since the last read of this register
Bit stuff error. The STUFFERR bit indicates whether or not the bit stuffing that occurred in
the last transmitted or received message was correct.
0 = No bit stuffing error was detected since the last read of this register
1 = A bit stuffing error was detected since the last read of this register
Transmit error status flag. The TXWARN status flag reflects the status of the TouCAN trans-
mit error counter.
0 = Transmit error counter < 96
1 = Transmit error counter ≥ 96
Receiver error status flag. The RXWARN status flag reflects the status of the TouCAN re-
ceive error counter.
0 = Receive error counter < 96
1 = Receive error counter ≥ 96
Idle status. The IDLE bit indicates when there is activity on the CAN bus.
0 = The CAN bus is not idle
1 = The CAN bus is idle
Transmit/receive status. The TX/RX bit indicates when the TouCAN module is transmitting
or receiving a message. TX/RX has no meaning when IDLE = 1.
0 = The TouCAN is receiving a message if IDLE = 0
1 = The TouCAN is transmitting a message if IDLE = 0
Fault confinement state. The FCS[1:0] field describes the state of the TouCAN. Refer to
ble
If the SOFTRST bit in CANMCR is asserted while the TouCAN is in the bus off state, the
error and status register is reset, including FCS[1:0]. However, as soon as the TouCAN exits
reset, FCS[1:0] bits will again reflect the bus off state. Refer
more information on entry into and exit from the various fault confinement states.
Reserved
Bus off interrupt. The BOFFINT bit is used to request an interrupt when the TouCAN enters
the bus off state.
0 = No bus off interrupt requested
1 = When the TouCAN state changes to bus off, this bit is set, and if the BOFFMSK bit in
16-23.
CANCTRL0 is set, an interrupt request is generated. This interrupt is not requested after
reset.
Freescale Semiconductor, Inc.
Table 16-21 ESTAT Bit Descriptions
For More Information On This Product,
Table
CAN 2.0B CONTROLLER MODULE
16-22.
Go to: www.freescale.com
Rev. 15 October 2000
Description
to16.3.4 Error Counters
MOTOROLA
16-33
for
Ta-