MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 670

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

19.5 Programming the CMF Array
19.5.1 Program Sequence
MPC555
USER’S MANUAL
To modify the charge stored in the isolated element of the CMF bit from a logic one
state to a logic zero state, a programming operation is required. This programming
operation applies the required voltages to change the charge state of the selected bits
without changing the logic state of any other bits in the CMF array. The program oper-
ation cannot change the logic zero state to a logic one state; this must be done by the
erase operation. Programming uses a set of program buffers of 64 bytes each to store
the required data, an address offset buffer to store the starting address of the block(s)
to be programmed and a block select buffer that stores information on which block(s)
are to be programmed. Any number of the array blocks may be programmed at one
time.
If block M of the CMF EEPROM is protected (PROTECT[M] = 1), it will not be pro-
grammed. Also, if EPEE = 0, no programming voltages will be applied to the array.
Software should verify the state of EPEE prior to programming (programming will fail
if EPEE = 0). The user should also insure that the programming voltage (5.0 ± 0.25
volts) is applied to VPP.
The CMF EEPROM module requires a sequence of writes to the high voltage control
register (CMFCTL) and to the programming page buffer(s) in order to enable the high
voltage to the array or shadow information for program operation. See
the programming algorithm bit settings.
The required program sequence follows.
1. Write PROTECT[0:7] to disable protection on blocks to be programmed.
2. Write PAWS to 0b100, write NVR = 1, write GDB = 1.
3. Using
4. Write SES = 1 in the CMFCTL register.
/
— Pulse width timing control fields for a program pulse
— BLOCK[0:7] to select the array blocks to be programmed
— PE = 0 in the CMFCTL register
MPC556
gram the following fields:
Do not program any page more than once after a successful erase
operation. While this will not physically damage the array it will cause
an increased partial disturb time for the unselected bits on the row
and columns that are not programmed. If this happens, a full erase of
all blocks being programmed must be done before the CMF
EEPROM can be used reliably.
Step 4 can be accomplished with the same write as that in step 3. It
is listed as a separate step in the sequence for looping.
19.7.6 A Technique to Determine SCLKR, CLKPE, and
Freescale Semiconductor, Inc.
For More Information On This Product,
CDR MoneT FLASH EEPROM
Go to: www.freescale.com
Rev. 15 October 2000
WARNING
NOTE
Table 19-4
CLKPM, pro-
MOTOROLA
19-18
for