MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 656

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

19.2 Programming Model
19.2.1 CMF EEPROM Control Registers
MPC555
USER’S MANUAL
The CMF EEPROM Module consists of two addressed sections. The first is the 32-
byte control registers used to configure, program, erase and test the CMF EEPROM
array while, the second is the array.
Figure 19-1
arrays and control registers. Refer to
complete memory map.
0x06 FFFF
The control registers are used to control CMF EEPROM module operation. They re-
side in supervisor data space. On master reset the registers are loaded with default
reset information. Some of the registers are special CMF NVM registers which retain
their state when power is removed from the CMF EEPROM. These special FLASH
NVM registers are identified in the individual register field and control bit descriptions.
The CMF EEPROM control registers are accessible for read or write operation at all
times while the device is powered up except during master reset, soft reset or erase
interlock write.
The access time of a CMF register is one system clock for both read and write access-
es. Accesses to reserved registers will cause the BIU to generate a data error excep-
tion.
0x08 0000
0x 2F
0x 2F C 000
0x 2F
0x00 0000
/
BFFF
FFFF
MPC556
Figure 19-1 CMF Array and Control Register Addressing
shows the part of the MPC555 / MPC556 memory map involving the CMF
(2.6 Mbytes – 16 Kbytes)
U SI U & F lash
Reserved for Flash
CMF Flash
448
Freescale Semiconductor, Inc.
16 Kbytes
For More Information On This Product,
Kbytes
CDR MoneT FLASH EEPROM
Control
Go to: www.freescale.com
Rev. 15 October 2000
1.3 MPC555 / MPC556 Address Map
FLASH Module B (64 bytes)
FLASH Module A (64 bytes)
USIU Control Registers
Reserved for SIU
1 Kbyte
0x2F C000
0x2F C800
0x2F C840
0x2F C880
MOTOROLA
for the
19-4