MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 478

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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14.7.1.1 QSPI Control Register 0
SPCR0 — QSPI Control Register 0
MPC555
USER’S MANUAL
Access
RESET:
NOTES:
MSTR
MSB
S/U
S/U
S/U
S/U
S/U
S/U
S/U
1. S = Supervisor access only
2. 8-bit registers, such as SPCR3 and SPSR, are on 8-bit boundaries. 16-bit registers such as SPCR0 are on 16-bit
0
0
To ensure proper operation, set the QSPI enable bit (SPE) in SPCR1 only after initial-
izing the other control registers. Setting this bit starts the QSPI.
Rewriting the same value to a control register does not affect QSPI operation with the
exception of writing NEWQP in SPCR2. Rewriting the same value to these bits causes
the RAM queue pointer to restart execution at the designated location.
Before changing control bits, the user should halt the QSPI. Writing a different value
into a control register other than SPCR2 while the QSPI is enabled may disrupt oper-
ation. SPCR2 is buffered, preventing any disruption of the current serial transfer. After
the current serial transfer is completed, the new SPCR2 value becomes effective.
SPCR0 contains parameters for configuring the QSPI before it is enabled. The CPU
has read/write access to SPCR0, but the QSPI has read access only. SPCR0 must be
initialized before QSPI operation begins. Writing a new value to SPCR0 while the
QSPI is enabled disrupts operation.
S/U = Supervisor access only or unrestricted user access (assignable data space).
boundaries.
1
WOM
/
0x30 51C0 –
0x30 5140 –
0x30 5180 –
0x30 501E/
0x30 51DF
0x30 501A
0x30 501C
0x30 501F
0x30 517F
0x30 51BF
0x30 5018
Q
1
0
MPC556
Address
2
0
MSB
3
0
BITS
See
2
Freescale Semiconductor, Inc.
QSPI Control Register 3 (SPCR3)
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
4
0
Table 14-17
Table 14-12 QSPI Register Map
5
0
Go to: www.freescale.com
Rev. 15 October 2000
CPOL CPHA
for bit descriptions.
6
0
See
See
See
Transmit Data RAM (32 half-words)
Receive Data RAM (32 half-words)
QSPI Control Register 0 (SPCR0)
QSPI Control Register 1 (SPCR1)
QSPI Control Register 2 (SPCR2)
7
1
Table 14-13
Table 14-15
Table 14-16
Command RAM (32 bytes)
8
0
9
0
for bit descriptions.
for bit descriptions.
for bit descriptions.
10
See
0
QSPI Status Register (SPSR)
Table 14-18
11
0
SPBR
12
0
for bit descriptions.
13
1
0x30 5018
MOTOROLA
14
0
14-16
LSB
15
LSB
0

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