MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 357

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

10.2.3 Write-Protect Configuration
10.2.4 Address and Address Space Checking
10.2.5 Burst Support
MPC555
USER’S MANUAL
or words on word boundaries. The port size is specified by the PS bits in the base reg-
ister.
The WP bit in each base register can restrict write access to its range of addresses.
Any attempt to write this area results in the associated WPER bit being set in the
MSTAT.
If an attempt to access an external device results in a write-protect violation, the mem-
ory controller considers the access to be no match. No chip-select line is asserted ex-
ternally, and the memory controller does not terminate the cycle. The external bus
interface generates a normal cycle on the external bus. Since the memory controller
does not acknowledge the cycle internally, the cycle may be terminated by external
logic asserting TA or by the on-chip bus monitor asserting TEA.
The base address is written to the BR. The address mask bits for the address are writ-
ten to the OR. The address type access value, if desired, is written to the AT bits in the
BR. The ATM bits in the OR can be used to mask this value. If address type checking
is not desired, program the ATM bits to zero.
Each time an external bus cycle access is requested, the address and address type
are compared with each one of the banks. If a match is found, the attributes defined
for this bank in its BR and OR are used to control the memory access. If a match is
found in more than one bank, the lowest bank matched handles the memory access
(e.g., bank zero is selected over bank one). Note that when an external master access-
es a slave on the bus, the internal AT[0:2] lines reaching the memory controller are
forced to 100.
Burst support is for read only. The memory controller supports burst accesses of ex-
ternal burstable memory. To enable bursts, clear the BI in the appropriate base regis-
ter.
Bursts are four beats and non-wrapping. That is, the memory controller executes up
to four one-word accesses, but when a modulo four limit is reached, the burst is termi-
nated (even if fewer than four words have been accessed).
When the SIU initiates a burst access, if no match is found in any of the memory con-
troller’s regions then a burst access is initiated to the external bus. The termination of
each beat for this access is externally controlled (i.e., the user is responsible for termi-
nating each data beat using the bus termination protocol).
To support different types of memory devices, the memory controller supports two
types of timing for the BDIP signal: normal and late. Note that the BDIP pin itself is con-
trolled by the external bus interface logic. Refer to
SECTION 9 EXTERNAL BUS
/
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MEMORY CONTROLLER
INTERFACE.
Rev. 15 October 2000
Figure 9-13
and
Figure 9-14
MOTOROLA
10-5
in