MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 525

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
• Interrupt generation when the top half (SCTQ[0:7]) of the queue has been emp-
• Enable and disable options for the interrupts QTHE and QBHE as controlled by
• Programmable 4-bit register queue transmit size (QTSZ) for configuring the
• 4-bit status register to indicate the number of data transfers pending (QPEND).
• 4-bit counter (QTPNT) is used as a pointer to indicate the next data frame within
• A transmit complete (TC) bit re-defined when the queue is enabled (QTE = 1) to
• When the transmit queue is enabled (QTE = 1), writes to the transmit data register
/
than 16. This is achieved by the transmit wrap enable (QTWE) bit. When QTWE
is set, the hardware is allowed to restart transmitting from the top of the queue
(SCTQ[0]). After each wrap, QTWE is cleared by hardware.
tied (QTHE) and the bottom half (SCTQ[8:15]) of the queue has been emptied
(QBHE). This may allow for uninterrupted and continuous transmits by indicating
to the CPU that it can begin refilling the queue portion that is now emptied.
QTHEI and QBHEI respectfully.
queue to any size up to 16 transfers at a time. This value may be rewritten after
transmission has started to allow for the wrap feature.
This register counts down to all 0’s where the next count rolls over to all 1’s. This
counter is writable in test mode; otherwise it is read-only.
the transmit queue to be loaded into the SC1DR. This counter is writable in test
mode; otherwise it is read-only.
indicate when the entire queue (including when wrapped) is finished transmitting.
This is indicated when QPEND = 1111 and the shifter has completed shifting data
out. TC is cleared when the SCxSR is read with TC = 1 followed by a write to
SCTQ[0:15]. If the queue is disabled (QTE = 0), the TC bit operates as originally
designed.
(SC1DR) have no effect.
— Transmissions of more than 16 data frames must be performed in multiples of
— The QTHE bit is set by hardware when the top half is empty or the transmis-
— The QBHE bit is set by hardware when the bottom half is empty or the trans-
— In order to implement the transmit queue, QTE must be set (QSCI1CR), TE
MPC556
16 (QTSZ = 0b1111) except for the last set of transmissions. For any single
non-continuous transmissions of 16 or less or the last transmit set composed
of 16 or fewer data frames, the user is allowed to program QTSZ to the corre-
sponding value of 16 or less where QTWE = 0.
sion has completed. The QTHE bit is cleared when the QSCI1SR is read with
QTHE set, followed by a write of QTHE to zero.
mission has completed. The QBHE bit is cleared when the QSCI1SR is read
with QBHE set, followed by a write of QBHE to zero.
must be set (SCC1R1), QTHE must be cleared (QSCI1SR), and TDRE must
be set (SC1SR).
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
14-63