MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 372

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

10.4 Global (Boot) Chip-Select Operation
MPC555
USER’S MANUAL
Global (boot) chip-select operation allows address decoding for a boot ROM before
system initialization. CS[0] is the global chip-select output. Its operation differs from
that of the other external chip-select outputs following a system reset. When the RCPU
begins accessing memory after a system reset, CS[0] is asserted for every address,
unless an internal device (register) is accessed.
The global chip select provides a programmable port size at system reset using the
reset BPS pins ([4:5]) of the reset configuration word, allowing a boot ROM to be lo-
cated anywhere in the address space. For more information, see
Configuration
sponds to all address types. CS[0] operates in this way until the first write to the CS[0]
option register (OR0). The pin can be programmed to continue decoding a range of
addresses after this write, provided the preferred address range is first loaded into
base register zero. After the first write to OR0, the global chip select can only be re-
started with a system reset.
The memory controller operates in boot mode until the user modifies the values in OR0
and BR to the ones desired.
Table 10-3
/
MPC556
If the MPC555 / MPC556 is configured (in the reset configuration
word) to use the internal flash EEPROM as boot memory CS[0] is not
asserted.
shows the initial values of the “boot bank” in the memory controller.
Table 10-3 Boot Bank Fields Values After Hard Reset
Word. The global chip select does not provide write protection and re-
Freescale Semiconductor, Inc.
For More Information On This Product,
BSCY[0:2]
ATM
AM[0:16]
ACS[0:1]
SCY[0:3]
CSNT
SETA
TRLX
Field
WP
PS
BI
V
[
0:2]
Go to: www.freescale.com
MEMORY CONTROLLER
Rev. 15 October 2000
From reset configuration
From reset configuration
0 0000 0000 0000 0000
NOTE
Value (Binary)
1111
000
011
00
0
0
1
0
0
7.5.2 Hard Reset
MOTOROLA
10-20