MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 598

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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16.4.6 Overload Frames
16.5 Special Operating Modes
16.5.1 Debug Mode
MPC555
USER’S MANUAL
When the TouCAN receives a remote frame, it compares the remote frame ID to the
IDs of all transmit message buffers programmed with a code of 1010. If there is an ex-
act matching ID, the data frame in that message buffer is transmitted. If the RTR bit in
the matching transmit message buffer is set, the TouCAN transmits a remote frame as
a response.
A received remote frame is not stored in a receive message buffer. It is only used to
trigger the automatic transmission of a frame in response. The mask registers are not
used in remote frame ID matching. All ID bits (except RTR) of the incoming received
frame must match for the remote frame to trigger a response transmission.
The TouCAN does not initiate overload frame transmissions unless it detects the fol-
lowing conditions on the CAN bus:
The TouCAN module has three special operating modes:
Debug mode is entered when the FRZ1 bit in CANMCR is set and one of the following
events occurs:
Once entry into debug mode is requested, the TouCAN waits until an intermission or
idle condition exists on the CAN bus, or until the TouCAN enters the error passive or
bus off state. Once one of these conditions exists, the TouCAN waits for the comple-
tion of all internal activity. Once this happens, the following events occur:
• A dominant bit in the first or second bit of intermission
• A dominant bit in the seventh (last) bit of the end-of-frame (EOF) field in receive
• A dominant bit in the eighth (last) bit of the error frame delimiter or overload frame
• Debug mode
• Low-power stop mode
• Auto power save mode
• The HALT bit in the CANMCR is set; or
• The IMB3 FREEZE line is asserted
• The TouCAN stops transmitting or receiving frames
• The prescaler is disabled, thus halting all CAN bus communication
• The TouCAN ignores its Rx pins and drives its Tx pins as recessive
• The TouCAN loses synchronization with the CAN bus and the NOTRDY and
• The CPU is allowed to read and write the error counter registers
/
frames
delimiter
FRZACK bits in CANMCR are set
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
CAN 2.0B CONTROLLER MODULE
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
16-16

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