MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 459

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Bit(s)
10:15
0:5
8:9
6
7
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
CHAN
Name
BYP
IST
—
P
Reserved
Pause. The pause bit allows the creation of sub-queues within queue 1 and queue 2. The
QADC64 performs the conversion specified by the CCW with the pause bit set, and then the
queue enters the pause state. Another trigger event causes execution to continue from the pause
to the next CCW.
0 = Do not enter the pause state after execution of the current CCW.
1 = Enter the pause state after execution of the current CCW.
Sample amplifier bypass. Setting BYP enables the amplifier bypass mode for a conversion, and
subsequently changes the timing. Refer to
ing
0 = Amplifier bypass mode disabled.
1 = Amplifier bypass mode enabled.
Input sample time. The IST field specifies the length of the sample window. Longer sample times
permit more accurate A/D conversions of signals with higher source impedances, especially if
BYP = 1.
00 = QCKL period x 2
01 = QCKL period x 4
10 = QCKL period x 8
11 = QCKL period x 16
Channel number. The CHAN field selects the input channel number corresponding to the analog
input pin to be sampled and converted. The analog input pin channel number assignments and
the pin definitions vary depending on whether the QADC64 is operating in multiplexed or non-
multiplexed mode. The queue scan mechanism sees no distinction between an internally or ex-
ternally multiplexed analog input.
If CHAN specifies a reserved channel number (channels 32 to 47) or an invalid channel number
(channels 4 to 31 in non-multiplexed mode), the low reference level (VRL) is converted. Program-
ming the channel field to channel 63 indicates the end of the queue. Channels 60 to 62 are spe-
cial internal channels. When one of these channels is selected, the sample amplifier is not used.
The value of VRL, VRH, or (V
input sample time to any value other than two for one of the internal channels has no benefit ex-
cept to lengthen the overall conversion time.
Table 13-20
21
shows the channel number assignments for the multiplexed mode.
for more information.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 13-19 CCW Bit Descriptions
shows the channel number assignments for the non-multiplexed mode.
Go to: www.freescale.com
Rev. 15 October 2000
RH
– V
RL
)/2 is placed directly into the converter. Programming the
Description
13.9.1.1 Amplifier Bypass Mode Conversion Tim-
MOTOROLA
Table 13-
13-47