MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 231

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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6.13.1.3 External Master Control Register (EMCR)
MPC555
USER’S MANUAL
EMCR — External Master Control Register
Bit(s)
16:19
21:22
24:27
28:30
MSB
8:15
0:7
20
23
31
0
0
RESET:
The external master control register selects the external master modes and deter-
mines the internal bus attributes for external-to-internal accesses.
/
1
0
MASKNUM
PARTNUM
MPC556
Name
CLES
FLEN
ISB
2
0
3
0
This read-only field is mask programmed with a code corresponding to the part number of
the part on which the SIU is located. It is intended to help factory test and user code which
is sensitive to part changes. This changes when the part number changes. For example, it
would change if any new module is added, if the size of any memory module is changed. It
would not change if the part is changed to fix a bug in an existing module. The MPC555 /
MPC556 chip has an ID of 0x30.
This read-only field is mask programmed with a code corresponding to the mask number of
the part. It is intended to help factory test and user code which is sensitive to part changes.
Reserved
Flash enable is a read-write bit. The default state of FLEN is negated, meaning that the boot
is performed from external memory. This bit can be set at reset by the reset configuration
word.
0 = On-chip flash memory is disabled, and all internal cycles to the allocated flash address
1 = On-chip flash memory is enabled
Reserved
Core little-endian swap
0 = Little-endian swap logic in the EBI is not activated for RCPU accesses after reset
1 = Little-endian swap logic in the EBI is activated for RCPU accesses after reset
Reserved
This read-write field defines the base address of the internal memory space. The initial value
of this field can be configured at reset to one of eight addresses, and then can be changed
to any value by software. Internal base addresses are as follows:
000 = 0x0000 0000
001 = 0x0040 0000
010 = 0x0080 0000
011 = 0x00C0 0000
100 = 0x0100 0000
101 = 0x0140 0000
110 = 0x0180 0000
111 = 0x01C0 0000
Reserved
Freescale Semiconductor, Inc.
space are mapped to external memory
SYSTEM CONFIGURATION AND PROTECTION
4
0
For More Information On This Product,
Table 6-11 IMMR Bit Descriptions
5
0
Go to: www.freescale.com
Rev. 15 October 2000
6
0
RESERVED
7
0
8
0
Description
9
0
10
0
11
0
12
0
13
0
0x2F C030
MOTOROLA
14
0
15
6-23
0

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