MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 312

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.5.4 Burst Mechanism
MPC555
USER’S MANUAL
ed slave device must internally increment ADDR28 and ADDR29 (and ADDR30 in the
case of a 16-bit port slave device, and also ADDR31 in the case of an 8-bit port slave
device) of the supplied address for each transfer, causing the address to reach a four-
word boundary, and then stop. The address and transfer attributes supplied by the
MPC555 / MPC556 remain stable during the transfers. The selected device terminates
each transfer by driving or sampling the word on the data bus and asserting TA.
The MPC555 / MPC556 also supports burst-inhibited transfers for slave devices that
are unable to support bursting. For this type of bus cycle, the selected slave device
supplies or samples the first word the MPC555 / MPC556 points to and asserts the
burst-inhibit signal with TA for the first transfer of the burst access. The MPC555 /
MPC556 responds by terminating the burst and accessing the remainder of the 16-
byte block. These remaining accesses use up to three read/write bus cycles (each one
for a word) in the case of a 32-bit port width slave, up to seven read/write bus cycles
in the case of a 16-bit port width slave, or up to fifteen read/write bus cycles in the case
of a 8-bit port width slave.
The general case of burst transfers assumes that the external memory has a 32-bit
port size. The MPC555 / MPC556 provides an effective mechanism for interfacing with
16-bit port size memories and 8-bit port size memories allowing bursts transfers to
these devices when they are controlled by the internal memory controller.
In this case, the MPC555 / MPC556 attempts to initiate a burst transfer as in the normal
case. If the memory controller signals to the bus interface that the external device has
a small port size (8 or 16 bits), and if the burst is accepted, the bus interface completes
a burst of 8 or 16 beats.
Each of the data beats of the burst transfers effectively only one or two bytes. Note
that this burst of 8 or 16 beats is considered an atomic transaction, so the MPC555 /
MPC556 does not allow other unrelated master accesses or bus arbitration to inter-
vene between the transfers.
In addition to the standard bus signals, the MPC555 / MPC556 burst mechanism uses
the following signals:
At the start of the burst transfer, the master drives the address, the address attributes,
and the BURST signal to indicate that a burst transfer is being initiated, and asserts
TS. If the slave is burstable, it negates the burst-inhibit (BI) signal. If the slave cannot
burst, it asserts BI.
During the data phase of a burst write cycle the master drives the data. It also asserts
BDIP if it intends to drive the data beat following the current data beat. When the slave
has received the data, it asserts the signal transfer acknowledge to indicate to the
master that it is ready for the next data transfer. The master again drives the next data
• The BURST signal indicates that the cycle is a burst cycle.
• The burst data in progress (BDIP) signal indicates the duration of the burst data.
• The burst inhibit (BI) signal indicates whether the slave is burstable.
/
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
EXTERNAL BUS INTERFACE
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
9-16