MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 73

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

2.3.1.11 RD/WR
2.3.1.12 BURST
2.3.1.13 BDIP
2.3.1.14 TS
2.3.1.15 TA
2.3.1.16 TEA
MPC555
USER’S MANUAL
Transfer size – Indicates the size of the requested data transfer in the current bus cy-
cle.
Pin Name: rd_wr_b
Read/Write – Indicates the direction of the data transfer for a transaction. A logic one
indicates a read from a slave device; a logic zero indicates a write to a slave device.
Pin Name: burst_b
Burst Indicator – Indicates whether the current transaction is a burst transaction or
not.
Pin Name: bdip_b
Burst data in progress – Indicates to the slave that there is a data beat following the
current data beat.
Pin Name: ts_b
Transfer Start – Indicates the start of a bus cycle that transfers data to/from a slave
device. This signal is driven by the master only when it gained the ownership of the
bus. Every master should negate this signal before the bus relinquish. Every master
should negate this signal before the bus is relinquished. This pin is an active negate
signal and may need an external pull-up resistor to ensure proper operation and signal
timing specifications.
Pin Name: ta_b
Transfer Acknowledge – This line indicates that the slave device addressed in the
current transaction has accepted the data transferred by the master (write) or has driv-
en the data bus with valid data (read). The slave device negates the TA_B signal after
the end of the transaction and immediately three-state it to avoid contentions on the
line if a new transfer is initiated addressing other slave devices. This pin is an active
negate signal and may need an external pull-up resistor to ensure proper operation
and signal timing specifications.
Pin Name: tea_b
/
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
SIGNAL DESCRIPTIONS
Rev. 15 October 2000
MOTOROLA
2-15