MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 548

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

15.9 MIOS Counter Prescaler Submodule (MCPSM)
15.9.1 MIOS Counter Prescaler Submodule (MCPSM) Registers
MPC555
USER’S MANUAL
cording to this level, the ICS sets the correct IRQ[7:0] lines with the correct ILBS[1:0]
time multiplex lines on the peripheral bus. The CPU is then informed as to which of the
thirty-two interrupt levels is requested.
Based on the interrupt level requested, the software must determine which submodule
requested the interrupt. The software may use a find-first-one type of instruction to de-
termine, in the concerned MIRSM, which of the bits is set. The CPU can then serve
the requested interrupt.
The MIOS counter prescaler submodule (MCPSM) divides the MIOS1 clock (F
generate the counter clock. It is designed to provide all the submodules with the same
division of the main MIOS1 clock (division of F
The clock signal is prescaled by loading the value of the clock prescaler register into
the prescaler counter every time it overflows. This allows all prescaling factors be-
tween two and 16. Counting is enabled by asserting the PREN bit in the control regis-
ter. The counter can be stopped at any time by negating this bit, thereby stopping all
submodules using the output of the MCPSM (counter clock).
Table 15-9
/
MPC556
MCPSMSCR
is the address map for the MCPSM submodule.
Prescaler
Register
Clock
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Freescale Semiconductor, Inc.
Figure 15-3 MCPSM Block Diagram
For More Information On This Product,
PREN
CP0
CP1
CP2
CP3
Go to: www.freescale.com
Rev. 15 October 2000
f
Enable
SYS
Decrementer
4-bit
Dec.
SYS
Load
). It uses a 4-bit modulus counter.
= 1?
Counter Clock
MOTOROLA
SYS
15-12
) to